mc68hc908gp32 Freescale Semiconductor, Inc, mc68hc908gp32 Datasheet - Page 225
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mc68hc908gp32
Manufacturer Part Number
mc68hc908gp32
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908GP32.pdf
(266 pages)
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18.3.1.1 Normal Monitor Mode
When V
divide-by-two of the input clock. If PTC3 is high with V
bus frequency will be a divide-by-four of the input clock. Holding the PTC3 pin low when entering monitor
mode causes a bypass of a divide-by-two stage at the oscillator only if V
Freescale Semiconductor
Function
[Pin No.]
Monitor
Monitor
MON08
Normal
Forced
Mode
1. PTA0 must have a pullup resistor to V
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus
3. External clock is a 4.9152 MHz or 9.8304 MHz canned oscillator on OSC1 or a 32.768 kHz crystal on OSC1 and OSC2.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
User
frequency / 256.
TST
V
V
V
V
V
IRQ
V
V
[6]
or
TST
TST
TST
DD
DD
SS
SS
is applied to IRQ and PTC3 is low upon monitor mode entry, the bus frequency is a
OSC1
V
V
V
V
NC
NC
NC
NC
NC
NC
RST
RST
V
V
V
V
V
DD
[4]
or
or
or
TST
TST
TST
DD
DD
DD
DD
DD
Table 18-1. Monitor Mode Signal Requirements and Options
Vector
$FFFF
(blank)
$FFFF
(blank)
$FFFF
Reset
Not
11
13
15
—
X
X
1
3
5
7
9
Communication
PTA0
COM
[8]
10
12
14
16
X
1
1
1
1
2
4
6
8
Serial
DD
MC68HC908GP32 Data Sheet, Rev. 10
PTA7
SSEL
GND
RST
IRQ
PTA0
PTA7
PTC0
PTC1
PTC3
[10]
in monitor mode.
0
0
0
0
X
MOD0
PTC0 PTC1
[12]
Selection
X
X
X
1
1
Mode
MOD1
[14]
X
X
X
0
0
TST
Divider
PTC3
DIV4
applied to IRQ upon monitor mode entry, the
[16]
X
X
X
0
1
OFF Disabled
OFF Disabled
OFF Disabled
PLL
ON Disabled
—
X
Enabled
COP
—
TST
is applied to IRQ. In this
External
4.9152
9.8304
9.8304
32.768
Clock
OSC1
MHz
MHz
MHz
kHz
[13]
X
Communication
Monitor Module (MON)
Frequency
2.457 MHz
2.457 MHz
2.457 MHz
2.457 MHz
Speed
Bus
—
X
Baud
9600
9600
9600
9600
Rate
—
X
225
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