mc68hc908gp20 Freescale Semiconductor, Inc, mc68hc908gp20 Datasheet - Page 170

• Manufacturer Part Number: mc68hc908gp20
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

Advance Information
170
in the FLASH array is organized into pages within rows. There are eight
pages of memory per row with eight bytes per page. The minimum erase
block size is a single row, 64 bytes. Programming is performed on a per
page basis; eight bytes at a time. The address ranges for the user
memory and vectors are:
When programming the FLASH, just enough program time must be used
to program a page. Too much program time can result in a program
disturb condition, in which case an erased bit on the row being
programmed becomes unintentionally programmed. Program disturb is
avoided by using an iterative program and margin read technique known
as the smart page programming algorithm. The smart programming
algorithm is required whenever programming the array (see
Program/Margin Read
To avoid the program disturb issue, each row should not be programmed
more than eight times before it is erased. The eight program cycle
maximum per row aligns with the architecture’s eight pages of storage
per row. The margin read step of the smart programming algorithm is
used to ensure programmed bits are programmed to sufficient margin for
data retention over the device lifetime.
Row architecture for this array is:
Programming tools are available from Freescale. Contact your local
Freescale representative for more information.
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$B000–$FDFF; user memory
$FF80; block protect register
$FE08
$FFDC–$FFFF; These locations are reserved for user-defined
interrupt and reset vectors.
$B000-$B03F; row0
$B040-$B07F; row1
$B080-$B0BF; row2
----------------------------
$FFC0-$FFFF; row 319
;
FLASH control register
Operation).
MC68HC908GP20
Freescale Semiconductor
11.7 FLASH
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Rev 2.1