mc68hc908gp20 Freescale Semiconductor, Inc, mc68hc908gp20 Datasheet - Page 200

• Manufacturer Part Number: mc68hc908gp20
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

14.4 Functional Description
Advance Information
200
NOTE:
NOTE:
Figure 14-1
out of reset. The LVI module contains a bandgap reference circuit and
comparator. Clearing the LVI power disable bit, LVIPWRD, enables the
LVI to monitor V
enables the LVI module to generate a reset when V
voltage, V
enables the LVI to operate in stop mode. Setting the LVI 5-V or 3-V trip
point bit, LVI5OR3, enables the trip point voltage,V
configured for 5-V operation. Clearing the LVI5OR3 bit enables the trip
point voltage, V
points are shown in
After a power-on reset (POR) the LVI’s default mode of operation is 3 V.
If a 5-V system is used, the user must set the LVI5OR3 bit to raise the
trip point to 5-V operation. Note that this must be done after every power-
on reset since the default will revert back to 3-V mode after each power-
on reset. If the V
the 3-V mode trip voltage when POR is released, the part will operate
because V
care must be taken to ensure that V
after POR is released.
If the user requires 5-V mode and sets the LVI5OR3 bit after a power-on
reset while the V
MCU will immediately go into reset. The LVI in this case will hold the part
in reset until either V
which will release reset or V
re-trigger the power-on reset and reset the trip point to 3-V operation.
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration
register (MOR1). See
configuration bits. Once an LVI reset occurs, the MCU remains in reset
until V
reset. See
interaction between the SIM and the LVI. The output of the comparator
controls the state of the LVIOUT flag in the LVI status register (LVISR).
DD
rises above a voltage, V
TRIPF
TRIPF
19.4.2.5 Low-Voltage Inhibit (LVI) Reset
shows the structure of the LVI module. The LVI is enabled
. Setting the LVI enable in stop mode bit, LVISTOP,
TRIPF
DD
DD
defaults to 3-V mode after a POR. So, in a 5-V system
DD
voltage. Clearing the LVI reset disable bit, LVIRSTD,
Section 23. Preliminary Electrical
supply is below the 5-V mode trip voltage but above
supply is not above the V
DD
, to be configured for 3-V operation. The actual trip
8.3 Functional Description
goes above the rising 5-V trip point, V
DD
decreases to approximately 0 V which will
TRIPR
DD
is above the 5-V mode trip voltage
, which causes the MCU to exit
TRIPR
MC68HC908GP20
for details of the LVI’s
Freescale Semiconductor
TRIPF
for 5-V mode, the
DD
for details of the
falls below a
Specifications.
, to be
TRIPR
—
Rev 2.1
,