mc68hc908gp20 Freescale Semiconductor, Inc, mc68hc908gp20 Datasheet - Page 339

• Manufacturer Part Number: mc68hc908gp20
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908GP20
Freescale Semiconductor
—
Rev 2.1
DMAS —DMA Select Bit
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable
This read only bit has no effect on this version of the SPI. This bit
always reads as a 0.
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See
transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See
data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module
must be set to logic 1 between bytes. (See
the CPHA bit.
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. (See
the SPE bit.
0 = SPRF DMA and SPTE DMA service requests disabled
1 = Master mode
0 = Slave mode
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
(SPRF CPU and SPTE CPU interrupt requests enabled)
Figure 20-4
20.10 Resetting the
Figure 20-4
and
and
Figure
Figure
Figure
20-6.) To transmit
SPI.) Reset clears
20-12.) Reset sets
Advance Information
20-6.) To
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