mc68hc912bd32 Freescale Semiconductor, Inc, mc68hc912bd32 Datasheet - Page 211

• Manufacturer Part Number: mc68hc912bd32
• Description: 16-bit Device Composed Of Standard On-chip Peripherals
• Manufacturer: Freescale Semiconductor, Inc

GISR
$xx07
41-sibus
H/S-RESET
W
R
NOTE:
BIT 7
TXIF
0
Figure 43 General Interrupt Status Register (GISR)
TXIF — Transmit Interrupt Flag
The TXIF flag is cleared two CPU cycles after clearing of all IFLG bits,
i.e. the application software should not read the TXIF flag immediately
after clearing the IFLG bit(s).
OVRNIF — Receive FIFO Overrun Interrupt Flag
ERRIF — Message Format Error (CRC, Frame) Interrupt Flag
SYNEIF — SYNC Pulse Too Early Error Interrupt Flag
OVRNIF
BIT 6
This read-only bit will be set when any of the enabled (IENAn = 1)
transmit buffers is empty. It can be cleared by clearing the IFLG bit(s)
of the corresponding buffer(s). After soft reset the flag is set if there is
at least one transmit buffer configured. If TXIE is set, a general
interrupt is pending while this flag is set.
This bit will be set when a Receive FIFO overrun occurred. If enabled,
a general interrupt is pending while this flag is set.
This bit will be set when a Message Format Error (CRC Error, Frame
Error) occurred. If enabled, a general interrupt is pending while this
flag is set.
This bit will be set when a SYNC pulse too early error appears. If
enabled, a general interrupt is pending while this flag is set.
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0
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1 = At least one transmit buffer is empty.
0 = All transmit buffers are full.
1 = A Receive FIFO overrun has been detected.
0 = No Receive FIFO overrun has occurred.
1 = A Message Format Error has been detected.
0 = No Message Format Error has occurred.
1 = SYNC pulse to early error.
0 = No SYNC pulse to early error has occurred.
ERRIF
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BIT 5
0
Byteflight™ Module
SYNEIF
BIT 4
0
SYNLIF
BIT 3
0
ILLPIF
BIT 2
0
MC68HC912BD32 Rev 1.0
LOCKIF
Programmer’s Model
BIT 1
Byteflight™ Module
0
WAKEIF
BIT 0
0