mc68hc912bd32 Freescale Semiconductor, Inc, mc68hc912bd32 Datasheet - Page 247

• Manufacturer Part Number: mc68hc912bd32
• Description: 16-bit Device Composed Of Standard On-chip Peripherals
• Manufacturer: Freescale Semiconductor, Inc

INSTRUCTION — BDM Instruction Register (hardware command explanation)
INSTRUCTION –
Hardware
Instruction
Decode
13-dev
RESET:
BIT 7
H/F
0
DATA
6
0
CLKSW — Clock Switch
The INSTRUCTION register is written by the BDM hardware as a result
of serial data shifted in on the BKGD pin. It is readable and writable in
Special Peripheral mode on the parallel bus. It is discussed here for two
conditions: when a hardware command is executed and when a
firmware command is executed.
Read and write: all modes
. The hardware clears the INSTRUCTION register if 512 BCLK cycles
occur between falling edges from the host.
The bits in the BDM instruction register have the following meanings
when a hardware command is executed.
H/F — Hardware/Firmware Flag
DATA — Data Flag – Shows that data accompanies the command.
The WRITE_BD_BYTE@FF01 command that changes CLKSW
including 150 cycles after the data portion of the command should be
timed at the old speed. Beginning with the start of the next BDM
command, the new clock can be used for timing BDM
communications.
If ECLK rate is slower than BCLK rate, CLKSW is ignored and BDM
system is forced to operate with ECLK.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = BDM system operates with BCLK.
1 = BDM system operates with ECLK.
0 = Firmware command
1 = Hardware command
0 = No data
1 = Data follows the command
R/W
5
0
Go to: www.freescale.com
Development Support
BKGND
4
0
W/B
3
0
BD/U
2
0
1
0
0
MC68HC912BD32 Rev 1.0
Background Debug Mode
Development Support
BIT 0
0
0
$FF00