mc68hc912bd32 Freescale Semiconductor, Inc, mc68hc912bd32 Datasheet - Page 31
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mc68hc912bd32
Manufacturer Part Number
mc68hc912bd32
Description
16-bit Device Composed Of Standard On-chip Peripherals
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC912BD32.pdf
(292 pages)
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Port B
Port E
11-pins
in the address map in peripheral mode. Refer to
Input/Output.
Port B pins are used for address and data in expanded modes. The port
data register is not in the address map during expanded and peripheral
mode operation. When it is in the map, port B can be read or written at
anytime.
Register DDRB determines whether each port B pin is an input or output.
DDRB is not in the address map during expanded and peripheral mode
operation. Setting a bit in DDRB makes the corresponding bit in port B
an output; clearing a bit in DDRB makes the corresponding bit in port B
an input. The default reset state of DDRB is all zeroes.
When the PUPB bit in the PUCR register is set, all port B input pins are
pulled-up internally by an active pull-up device. This bit has no effect if
the port is being used in expanded modes as the pull-ups are inactive.
Setting the RDPB bit in register RDRIV causes all port B outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to
Input/Output.
Port E pins operate differently from port A and B pins. Port E pins are
used for bus control signals and interrupt service request signals. When
a pin is not used for one of these specific functions, it can be used as
general-purpose I/O. However, two of the pins (PE[1:0]) can only be
used for input, and the states of these pins can be read in the port data
register even when they are used for IRQ and XIRQ.
The PEAR register determines pin function, and register DDRE
determines whether each pin is an input or output when it is used for
general-purpose I/O. PEAR settings override DDRE settings. Because
PE[1:0] are input-only pins, only DDRE[7:2] have effect. Setting a bit in
the DDRE register makes the corresponding bit in port E an output;
clearing a bit in the DDRE register makes the corresponding bit in port E
an input. The default reset state of DDRE is all zeroes.
Freescale Semiconductor, Inc.
For More Information On This Product,
Pinout and Signal Descriptions
Go to: www.freescale.com
Pinout and Signal Descriptions
MC68HC912BD32 Rev 1.0
Bus Control and
Bus Control and
Port Signals
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