gc80c510 CORERIVER Semiconductor, gc80c510 Datasheet - Page 82

• Manufacturer Part Number: gc80c510
• Description: Eprom/rom 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

6.2.8.3 Interrupt Response Time
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate
service routine. This may or may not clear the flag which caused the interrupt. In case of timer
interrupts, the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the
appropriate timer service routine. In case of external interrupt, INT0B and INT1B, the flags are cleared
only if they are edge triggered. In case of UART interrupts, the flags are not cleared by hardware.
Watchdog timer interrupt flag WDIF have to be cleared by software. The hardware LCALL behaves
exactly like the software LCALL instruction. This instruction saves the Program Counter contents onto
the stack, but does not save the PSW. The PC is reloaded with the vector address of that interrupt
which caused the LCALL.
the RETI instruction the processor pops the stack and loads the PC with the contents at the top of the
stack. The user must take care that the status of the stack is restored to what is after the hardware
LCALL, if the execution is to return to the interrupted program. The processor does not notice anything
if the stack contents are modified and will proceed with execution from the address put back into PC.
Note that a RET instruction would perform exactly the same process as a RETI instruction, but it would
not inform the interrupt controller that the interrupt service routine is completed, and would leave the
controller still thinking that the service routine is underway.
interrupt and the instruction underway. In the case of external interrupts INT0B to INT3B, they are
sampled at S3 state of every machine cycle and then their corresponding interrupt flags IEx will be set
or cleared. The Timer 0 and 1 overflow flags are set at S3 state of the machine cycle in which overflow
has occurred. These flag values are polled only in the next machine cycle. If a request is active and all
three conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes four
machine cycles to be completed. Thus there is a minimum time of five machine cycles between the
interrupt flag being set and the interrupt service routine being executed.
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the
instruction being executed, then an additional delay is introduced. The maximum response time (if no
other interrupt is in service) occurs if the MiDAS1.1 family is performing a write to IE, IP, EIE, EIP, IPH
or EXIF and then executes a 4-machine cycle instruction. From the time an interrupt source is activated,
the longest reaction time is 11 machine cycles. This includes 1 machine cycle to detect the interrupt, 2
Execution continues from the vector address until an RETI instruction is executed. On execution of
The response time for each interrupt source depends on several factors, such as the nature of the
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
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Functional Description