isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 21

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
Interrupts can be masked globally by means of the INTENA bit of the DcMode
register (see
The active level and signalling mode of the INT output is controlled by the INTPOL
and INTLVL bits of the DcHardwareConfiguration register (see
settings after reset are active LOW and level mode. When pulse mode is selected, a
pulse of 166 ns is generated when the OR-ed combination of all interrupt bits
changes from logic 0 to logic 1.
Bits RESET, RESUME, EOT and SOF are cleared upon reading the DcInterrupt
register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated
DcEndpointStatus register.
Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the
current bus status when reading the DcInterrupt register.
SETUP and OUT token interrupts are generated after ISP1161’s DC has
acknowledged the associated data packet. In bulk transfer mode, ISP1161’s DC will
issue interrupts for every ACK received for an OUT token or transmitted for an IN
token.
In isochronous mode, an interrupt is issued upon each packet transaction. The
firmware must take care of timing synchronization with the host. This can be done via
the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the
DcInterruptEnable register. If a Start-Of-Frame is lost, PSOF interrupts are generated
every 1 ms. This allows the firmware to keep data transfer synchronized with the host.
After 3 missed SOF events ISP1161’s DC will enter ‘suspend’ state.
An alternative way of handling isochronous data transfer is to enable both the SOF
and the PSOF interrupts and disable the interrupt for each isochronous endpoint.
Table
Rev. 02 — 13 December 2002
82).
Full-speed USB single-chip host and device controller
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Table
ISP1161
84). Default
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