isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 70

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
10.4.5 Hc PInterruptEnable register (R/W: 25H/A5H)
Table 43:
The bits 6 to 0 in this register are the same as those in the Hc PInterrupt register.
They are used together with bit 0 (InterruptPinEnable) of the
HcHardwareConfiguration register to enable or disable the bits in the Hc PInterrupt
register.
On power-on, all bits in this register are masked with logic 0. This means no interrupt
request output on the interrupt pin INT1 can be generated.
When the bit is set to logic 1, the interrupt for the bit is not masked but enabled.
Code (Hex): 25 — read
Code (Hex): A5 — write
Bit
6
5
4
3
2
1
0
Hc PInterrupt register: bit description
Symbol
ClkReady
HC
Suspended
OPR_Reg
-
AllEOT
Interrupt
ATLInt
SOFITLInt
Rev. 02 — 13 December 2002
Description
0 — no event
1 — clock is ready. After a wake-up is sent, there is a wait for clock
ready. Maximum is 1 ms, and typical is 160 s.
0 — no event
1 — the HC has been suspended and no USB activity is sent from
the microprocessor for each ms. When the microprocessor wants
to suspend the HC, the microprocessor must write to the
HcControl register. And when all downstream devices are
suspended, then the HC stops sending SOF; the HC is suspended
by having the HcControl register written into.
0 — no event
1 — There are interrupts from HC side. Need to read HcControl
and HcInterrupt registers to detect type of interrupt on the HC (if
the HC requires the Operational register to be updated).
reserved
0 — no event
1 — implies that data transfer has been completed via PIO transfer
or DMA transfer. Occurrence of internal or external EOT will set
this bit.
0 — no event
1 — implies that the microprocessor must read ATL data from the
HC. This requires that the HcBufferStatus register must first be
read. The time for this interrupt depends on the number of clocks
bit set for USB activities in each ms.
0 — no event
1 — implies that SOF indicates the 1 ms mark. The ITL buffer that
the HC has handled must be read. To know the ITL buffer status,
the HcBufferStatus register must first be read. This is for the
microprocessor to get ISO data to or from the HC. For more
information, see the 6th paragraph of
Full-speed USB single-chip host and device controller
…continued
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Section
9.5.
ISP1161
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