isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 23

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isp1161bm

Manufacturer Part Number
isp1161bm
Description
Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
Manufacturer
NXP Semiconductors
Datasheet

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De-assertion of pin INT2 can be achieved in the following manner. Bits[23:8] of the
DcInterrupt register are endpoint interrupts. These interrupts are cleared on reading
their respective DcEndpointStatus register. Bits[7:0] of the DcInterrupt register are
bus status and EOT interrupts that are cleared on reading the DcInterrupt register.
Make sure that bit INTENA is set to logic 1 when you perform the clear interrupt
commands.
For more information on interrupt control, see
Section
13.3.6.
Rev. 02 — 13 December 2002
Full-speed USB single-chip host and device controller
Section
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
13.1.3,
Section 13.1.5
ISP1161
and
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