lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 306

• Manufacturer Part Number: lan9312
• Description: Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
14.4.2.12
BITS
15:8
7
6
5
4
3
2
1
0
RESERVED
INT7_MASK
This interrupt mask bit enables/masks the ENERGYON interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT6_MASK
This interrupt mask bit enables/masks the Auto-Negotiation interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT5_MASK
This interrupt mask bit enables/masks the remote fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT4_MASK
This interrupt mask bit enables/masks the Link Down (link status negated)
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT3_MASK
This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT2_MASK
This interrupt mask bit enables/masks the Parallel Detection fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT1_MASK
This interrupt mask bit enables/masks the Auto-Negotiation page received
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
RESERVED
Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
This read/write register is used to enable or mask the various Port x PHY interrupts and is used in
conjunction with the
Index (decimal): 30
Port x PHY Interrupt Source Flags Register
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
306
Size:
16 bits
(PHY_INTERRUPT_SOURCE_x).
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
SMSC LAN9312
DEFAULT
Datasheet
0b
0b
0b
0b
0b
0b
0b
-
-