lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 51

• Manufacturer Part Number: lan9312
• Description: Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
5.2.1
5.2.2
The following sections detail each category of interrupts and their related registers. Refer to
Chapter 14, "Register Descriptions," on page 166
1588 Time Stamp Interrupts
Multiple 1588 Time Stamp interrupt sources are provided by the LAN9312. The top-level 1588_EVNT
(bit 29) of the
occurred in the
The
status of all 1588 interrupt conditions. These include TX/RX 1588 clock capture indication on Ports
2,1,0, 1588 clock capture for GPIO[8:9] events, as well as 1588 timer interrupt indication.
In order for a 1588 interrupt event to trigger the external IRQ interrupt pin, the desired 1588 interrupt
event must be enabled in the
(1588_EVNT_EN) of the
enabled via bit 8 (IRQ_EN) of the
For additional details on the 1588 Time Stamp interrupts, refer to
on page
Switch Fabric Interrupts
Multiple Switch Fabric interrupt sources are provided by the LAN9312 in a three-tiered register
structure as shown in
(INT_STS)
Interrupt Pending Register
In turn, the
Register (SWE_IMR)
(Buffer Manager, Switch Engine, and Port 2,1,0 MACs).
The low-level Switch Fabric sub-module interrupt pending and mask registers of the Buffer Manager,
Switch Engine, and Port 2,1,0 MACs provide multiple interrupt sources from their respective sub-
modules. These low-level registers provide the following interrupt sources:
In order for a Switch Fabric interrupt event to trigger the external IRQ interrupt pin, the following must
be configured:
For additional details on the Switch Fabric interrupts, refer to
on page
Buffer Manager
Pending Register
—Status B Pending
—Status A Pending
Switch Engine
Pending Register
—Interrupt Pending
Port 2,1,0 MACs
Pending Register
—No currently supported interrupt sources. These registers are reserved for future use.
The desired Switch Fabric sub-module interrupt event must be enabled in the corresponding mask
register
Interrupt Mask Register (SWE_IMR)
Register (MAC_IMR_x)
The desired Switch Fabric sub-module interrupt event must be enabled in the
Interrupt Mask Register (SWE_IMR)
Bit 28 (SWITCH_INT_EN) of the
IRQ output must be enabled via bit 8 (IRQ_EN) of the
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)
160.
81.
(Buffer Manager Interrupt Mask Register (BM_IMR)
provides indication that a Switch Fabric interrupt event occurred in the
Switch Engine Interrupt Pending Register (SWE_IPR)
Interrupt Status Register (INT_STS)
1588 Interrupt Status and Enable Register
(Switch Engine Interrupt Mask Register (SWE_IMR)
(Buffer Manager Interrupt Mask Register (BM_IMR)
provide status and enabling/disabling of all Switch Fabric sub-modules interrupts
(BM_IPR))
(SWE_IPR))
(MAC_IPR_x))
(Port x MAC Interrupt Mask Register (MAC_IMR_x)
Figure
Interrupt Enable Register (INT_EN)
(SWE_IPR).
for the Port 2,1,0 MACs)
5.1. The top-level SWITCH_INT (bit 28) of the
1588 Interrupt Status and Enable Register
Interrupt Configuration Register
DATASHEET
Interrupt Enable Register (INT_EN)
for the Switch Engine, and/or
51
for bit-level definitions of all interrupt registers.
provides indication that a 1588 interrupt event
Interrupt Configuration Register (IRQ_CFG)
(1588_INT_STS_EN).
must be set, and IRQ output must be
Section 6.6, "Switch Fabric Interrupts,"
for the Buffer Manager,
Section 11.6, "IEEE 1588 Interrupts,"
(IRQ_CFG).
and
provides enabling/disabling and
Port x MAC Interrupt Mask
Switch Engine Interrupt Mask
and
and
must be set
(1588_INT_STS_EN), bit 29
and
Buffer Manager Interrupt
Switch Engine Interrupt
Interrupt Status Register
Port x MAC Interrupt
Revision 1.2 (04-08-08)
Switch Engine
Switch Engine
Switch Engine