lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 448

• Manufacturer Part Number: lan9312
• Description: Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
15.5.5
A[x:5], END_SEL
SYMBOL
t
t
t
t
t
t
t
t
csdv
acyc
t
asu
adv
don
doff
doh
csh
ah
nCS, nRD
D[31:0]
A[4:2]
PIO Burst Read Cycle Timing
Please refer to
Note: A host PIO burst read cycle begins when both nCS and nRD are asserted. The cycle ends
Note:
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD Valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
when either or both nCS and nRD are de-asserted. These signals may be asserted and de-
asserted in any order.
Fresh data is supplied each time A[2] toggles.
t
asu
Section 8.4.5, "PIO Burst Reads," on page 107
Table 15.9 PIO Burst Read Cycle Timing Values
t
don
Figure 15.5 PIO Burst Read Cycle Timing
t
DESCRIPTION
acyc
t
csdv
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
t
adv
t
acyc
448
t
adv
for a functional description of this mode.
MIN
13
45
0
0
0
0
t
adv
t
acyc
t
TYP
ah
t
doh
t
MAX
doff
t
30
40
csh
9
SMSC LAN9312
Datasheet
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS