xccace-tq144 Xilinx Corp., xccace-tq144 Datasheet - Page 15

• Manufacturer Part Number: xccace-tq144
• Description: Ic Ace Controller Chip Tq144
• Manufacturer: Xilinx Corp.

Multiple Register Read Timing
The minimum timing requirements for sequential register read cycles are shown in
identical to single read cycles, except that the chip enable (MPCE) and write enable (MPWE) signals do not need to be
de-asserted between read cycles.
DS080 (v2.0) October 1, 2008
Product Specification
R
CYCLE
CLK
MPA
MPD
MPCE
MPWE
MPOE
Cycle 0
tSWE
tSCE
tSA
Figure 11: Multiple WORD Reads From ACE Register(s)
50ns
tDOE
ADDRESS <0>
Cycle 1
tDD
tDOE
Cycle 2
100ns
tSOE
DATA <0>
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tDD
tDOE
Cycle 3
tH
tH
tSOE
tSA
150ns
ADDRESS <1>
Cycle 4
tH
tDD
tDOE
Cycle 5
System ACE CompactFlash Solution
tSOE
DATA <1>
Figure
200ns
11. Sequential read cycles are
tDD
tDOE
tDOE
Cycle 6
tH
tH
tH
tH
tSOE
DS080_16_013101
Cycle 7
tH
250 0
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