xccace-tq144 Xilinx Corp., xccace-tq144 Datasheet - Page 17

• Manufacturer Part Number: xccace-tq144
• Description: Ic Ace Controller Chip Tq144
• Manufacturer: Xilinx Corp.

Data Buffer Read Cycle Ready Timing
When the data buffer is in read mode and the last data word
is read from the buffer, the data buffer ready signal will go
inactive (MPBRDY = LOW) two clock cycles following the
last clock cycle that the output enable is active (MPOE =
DS080 (v2.0) October 1, 2008
Product Specification
R
CYCLE
CLK
MPA
MPD
MPCE
MPWE
MPOE
MPBRDY
Figure 13: Valid and Invalid Reads From DATABUFREG Data Buffer
Cycle 0
tSWE
tSCE
tSA
50ns
DATABUFREG ADDRESS
tDOE
Cycle 1
tDD
tDOE
Cycle 2
VALID DATA
100ns
tSOE
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tDD
tDOE
Cycle 3
tH
tH
tSOE
tSA
LOW). Any attempt to read data out of an “empty” data
buffer (MPOE = LOW while MPBRDY = LOW) results in
invalid data. Valid and invalid data buffer reads are shown in
Figure
DATABUFREG ADDRESS
150ns
13.
tDBRDY
Cycle 4
tH
tDD
tDOE
INVALID DATA
Cycle 5
System ACE CompactFlash Solution
tSOE
200ns
tDD
tDOE
tDOE
Cycle 6
tH
tH
tH
tH
tSOE
DS080_18_020101
Cycle 7
tH
250
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