cyv15g0403tb Cypress Semiconductor Corporation., cyv15g0403tb Datasheet
cyv15g0403tb
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cyv15g0403tb Summary of contents
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... CYV15G0403TB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices. Each channel of the CYV15G0403TB Quad HOTLink II device independently accepts scrambled 10-bit transmission characters. These characters are serialized and output from ...
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... CYV15G0403TB Serializer Logic Block Diagram x10 Phase Align Buffer Serializer TX Document #: 38-02104 Rev. *B x10 x10 x10 Phase Phase Phase Align Align Align Buffer Buffer Buffer Serializer Serializer Serializer CYV15G0403TB Page [+] Feedback ...
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... Bit-Rate Clock D Transmit PLL Transmit PLL OE[2..1]D Clock Multiplier D Clock Multiplier Character-Rate Clock D TXBISTD PABRSTD CYV15G0403TB = Internal Signal RESET OE[2..1]A OUTA1+ OUTA1– OUTA2+ OUTA2– OE[2..1]B OUTB1+ OUTB1– OUTB2+ OUTB2– OE[2..1]C OUTC1+ OUTC1– OUTC2+ OUTC2– OE[2..1]D OUTD1+ OUTD1– ...
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... JTAG and Device Configuration and Control Block Diagram WREN Device Configuration ADDR[3:0] and Control Interface DATA[4:0] Document #: 38-02104 Rev. *B TXRATE[A..D] TXCKSEL[A..D] JTAG PABRST[A..D] Boundary TXBIST[A..D] Scan OE[2..1][A..D] Controller GLEN[11..0] FGLEN[2..0] CYV15G0403TB = Internal Signal RESET TRST TMS TCLK TDI TDO Page [+] Feedback ...
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... DA[1] ADDR REF TX NC GND NC GND [2] CLKD+ CLKOA ADDR ADDR TX NC GND NC GND [3] [1] ERRA GND NC GND CLKOD CLKA CYV15G0403TB OUT OUT OUT GND A2– B1– B2– OUT OUT OUT A2+ B1+ ...
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... TX TX REF ADDR GND NC GND DA[3] CLKOA CLKD+ [ ADDR ADDR GND NC GND DA[2] ERRA [1] [ GND NC GND DA[0] CLKA CLKOD CYV15G0403TB OUT OUT OUT D1– C2– C1– OUT OUT OUT D1+ C2+ ...
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... Pin Definitions CYV15G0403TB Quad HOTLink II Serializer Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDA[9:0] LVTTL Input, Transmit Data Inputs. TXDx[9:0] data inputs are captured on the rising edge of the TXDB[9:0] synchronous, transmit interface clock. The transmit interface clock is selected by the TXCKSELx latch ...
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... Pin Definitions (continued) CYV15G0403TB Quad HOTLink II Serializer Name I/O Characteristics Signal Description Device Configuration and Control Bus Signals WREN LVTTL input, Control Write Enable. The WREN input writes the values of the DATA[4:0] bus into the asynchronous, latch specified by the address location on the ADDR[3:0] bus. ...
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... TXCLKOx. Each clock multiplier PLL can accept a REFCLKx± input between 19.5 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYV15G0403TB clock multiplier (TXRATEx) and by the level on the associated SPDSELx input. [4] ...
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... Device Configuration and Control Interface The CYV15G0403TB is highly configurable via the configu- ration interface. This interface allows the device to be configured globally or allows each channel to be configured independently. Table 2 lists the configuration latches within the device including the initialization value of the latches upon the assertion of RESET ...
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... Set the static latch banks for the target channel. May be performed using a global operation, if the application permits it. Document #: 38-02104 Rev. *B CYV15G0403TB 3. Set the dynamic bank of latches for the target channel. Enable the output drivers. May be performed using a global operation, if the application permits it. [Required step.] 4 ...
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... D D4 (1111b) JTAG Support The CYV15G0403TB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan, and bypass are supported. This capability is present only on the LVTTL inputs and outputs and the REFCLKx± clock input. The high-speed serial inputs and outputs are not part of the JTAG test chain ...
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... Document #: 38-02104 Rev. *B Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYV15G0403TB requires one power-supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Operating Range + 0.5V Range ...
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... LVTTL Output Test Load 3.0V 2.0V 2. 1.4V th 0.8V 0.8V GND ≤ (c) LVTTL Input Test Waveform CYV15G0403TB AC Electrical Characteristics Parameter CYV15G0403TB Transmitter LVTTL Switching Characteristics Over the Operating Range f TXCLKx Clock Cycle Frequency TS t TXCLKx Period=1/f TXCLK TS [14] t TXCLKx HIGH Time TXCLKH [14] t TXCLKx LOW Time ...
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... JTAG Test Clock Period TCLK CYV15G0403TB Device RESET Characteristics Over the Operating Range t Device RESET Pulse Width RST CYV15G0403TB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range Parameter t Bit Time B [14] t CML Output Rise Time 20−80% (CML Test Load) ...
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... Capacitance Parameter Description C TTL Input Capacitance INTTL C PECL input Capacitance INPECL CYV15G0403TB HOTLink II Transmitter Switching Waveforms Transmit Interface t Write Timing TXCLKH TXCLKx selected TXCLKx TXDx[9:0] Transmit Interface Write Timing REFCLKx selected t REFH TXRATEx = 0 REFCLKx TXDx[9:0] Transmit Interface Write Timing REFCLKx selected ...
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... CYV15G0403TB HOTLink II Transmitter Switching Waveforms Transmit Interface TXCLKOx Timing t TXRATEx = 0 REFCLKx Note 22 TXCLKOx CYV15G0403TB HOTLink II Bus Configuration Switching Waveforms Bus Configuration Write Timing ADDR[3:0] DATA[4:0] WREN Note: 22. The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx± input. Document #: 38-02104 Rev. *B ...
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... POWER E04 VCC POWER E17 VCC POWER E18 VCC POWER E19 VCC POWER E20 VCC POWER F01 NC NO CONNECT CYV15G0403TB Ball ID Signal Name Signal Type F17 NC NO CONNECT F18 NC NO CONNECT F19 TXCLKOB LVTTL OUT F20 NC NO CONNECT G01 TXDC[7] LVTTL IN ...
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... VCC POWER V17 NC NO CONNECT V18 NC NO CONNECT V19 NC NO CONNECT V20 NC NO CONNECT W01 TXDD[5] LVTTL IN W02 TXDD[7] LVTTL IN CYV15G0403TB Ball ID Signal Name Signal Type L20 TXDB[6] LVTTL IN M01 NC NO CONNECT M02 NC NO CONNECT W03 NC NO CONNECT W04 NC NO CONNECT ...
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... Cypress against all charges Package Name Package Type BL256 256-Ball Thermally Enhanced Ball Grid Array BL256 Pb-Free 256-Ball Thermally Enhanced Ball Grid Array CYV15G0403TB Operating Range Commercial Commercial 51-85123-*E Page [+] Feedback ...
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... Document History Page Document Title: CYV15G0403TB Independent Clock Quad HOTLink II™ Serializer Document Number: 38-02104 ISSUE REV. ECN NO. DATE ** 246850 See ECN *A 338721 See ECN *B 384307 See ECN Document #: 38-02104 Rev. *B ORIG. OF CHANGE DESCRIPTION OF CHANGE FRE New Data Sheet SUA Added Pb-Free package option availability ...