cyv15g0403tb Cypress Semiconductor Corporation., cyv15g0403tb Datasheet - Page 12

• Manufacturer Part Number: cyv15g0403tb
• Description: Independent Clock Quad Hotlink Ii Serializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02104 Rev. *B
Table 3. Device Control Latch Configuration Table
JTAG Support
The CYV15G0403TB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the REFCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
(0000b)
(0001b)
(0010b)
(0011b)
(0100b)
(0101b)
(0110b)
(0111b)
(1000b)
(1001b)
(1010b)
(1011b)
(1100b)
(1101b)
(1110b)
(1111b)
ADDR
10
12
13
14
15
11
0
1
2
3
4
5
6
7
8
9
GLOBAL
GLOBAL
GLOBAL
Channel
MASK
A
A
A
B
B
B
C
C
C
D
D
D
Type
D
D
D
D
D
D
S
S
S
S
S
S
S
S
S
S
TXBISTGL
TXBISTB
TXBISTC
TXBISTD
TXBISTA
DATA4
D4
X
X
X
X
X
X
X
X
X
X
DATA3
OE2GL
OE2A
OE2B
OE2C
OE2D
D3
X
X
X
X
X
0
0
0
0
0
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0403TB is ‘0C810069’x.
TXCKSELGL
TXCKSELC
TXCKSELD
TXCKSELA
TXCKSELB
OE1GL
DATA2
OE1C
OE1D
OE1A
OE1B
D2
0
0
0
0
0
TXRATEGL
PABRSTGL
PABRSTC
PABRSTD
TXRATEA
PABRSTA
TXRATEB
PABRSTB
TXRATEC
TXRATED
DATA1
D1
X
X
X
X
X
CYV15G0403TB
GLEN10
FGLEN0
FGLEN1
FGLEN2
GLEN11
GLEN0
GLEN1
GLEN2
GLEN3
GLEN4
GLEN5
GLEN6
GLEN7
GLEN8
GLEN9
DATA0
D0
Page 12 of 21
Reset
Value
01101
10011
01101
10011
01101
10011
01101
10011
11111
11111
11111
11111
11111
N/A
N/A
N/A
[+] Feedback