cyv15g0403tb Cypress Semiconductor Corporation., cyv15g0403tb Datasheet - Page 11

• Manufacturer Part Number: cyv15g0403tb
• Description: Independent Clock Quad Hotlink Ii Serializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02104 Rev. *B
Table 2. Device Configuration and Control Latch Descriptions
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
TXCKSELA
TXCKSELB
TXCKSELC
TXCKSELD
TXRATEA
TXRATEB
TXRATEC
TXRATED
TXBISTA
TXBISTB
TXBISTC
TXBISTD
OE2A
OE2B
OE2C
OE2D
OE1A
OE1B
OE1C
OE1D
PABRSTA
PABRSTB
PABRSTC
PABRSTD
GLEN[11..0]
FGLEN[2..0]
1. Pulse RESET Low after device power-up. This operation
2. Set the static latch banks for the target channel. May be
Name
resets all four channels.
performed using a global operation, if the application
permits it.
Transmit Clock Select. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input
register TXDx[9:0] is clocked by REFCLKx↑. In this mode, the phase alignment buffer in the transmit
path is bypassed. When TXCKSELx = 0, the associated TXCLKx↑ is used to clock in the input register
TXDx[9:0].
Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used
to select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the
associated REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the
TXCLKOx output clocks are full-rate clocks and follow the frequency and duty cycle of the associated
REFCLKx± input. When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input
by 20 to generate the serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice
the frequency rate of the REFCLKx± input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data
Inputs are captured using both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx =
LOW, is an invalid state and this combination is reserved.
Transmit Bist Disabled. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit
BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When
TXBISTx = 0, the transmit BIST function is enabled.
Secondary Differential Serial Data Output Driver Enable. The initialization value of the OE2x latch =
0. OE2x selects if the OUT2x± secondary differential output drivers are enabled or disabled. When OE2x
= 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit
shifter. When OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled
via the configuration interface, it is internally powered down to reduce device power. If both serial drivers
for a channel are in this disabled state, the associated internal logic for that channel is also powered
down. A device reset (RESET sampled LOW) disables all output drivers.
Primary Differential Serial Data Output Driver Enable. The initialization value of the OE1x latch = 0.
OE1x selects if the OUT1x± primary differential output drivers are enabled or disabled. When OE1x = 1,
the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.
When OE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via the
configuration interface, it is internally powered down to reduce device power. If both serial drivers for a
channel are in this disabled state, the associated internal logic for that channel is also powered down.
A device reset (RESET sampled LOW) disables all output drivers.
Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx
is written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.
PABRST is an asynchronous input, but is sampled by each TXCLKx↑ to synchronize it to the internal
clock domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete
the initialization of the Phase Alignment Buffer.
Global Enable. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several
channels simultaneously in applications where several channels may have the same configuration. When
GLENx = 1 for a given address, that address is allowed to participate in a global configuration. When
GLENx = 0 for a given address, that address is disabled from participating in a global configuration.
Force Global Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a
GLobal ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global
channel, FGLEN forces the global update of the target latch banks.
Signal Description
3. Set the dynamic bank of latches for the target channel.
4. Reset the Phase Alignment Buffer for the target channel.
Enable the output drivers. May be performed using a global
operation, if the application permits it. [Required step.]
May be performed using a global operation, if the appli-
cation permits it. [Optional if phase align buffer is
bypassed.]
CYV15G0403TB
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