cyv15g0403tb Cypress Semiconductor Corporation., cyv15g0403tb Datasheet - Page 10

• Manufacturer Part Number: cyv15g0403tb
• Description: Independent Clock Quad Hotlink Ii Serializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02104 Rev. *B
By connecting the REFCLKx– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKx+ input for alternate logic levels. When doing so, it
is necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50Ω transmission lines. These drivers accept data from the
Transmit Shifter, which shifts the data out LSB first. These
drivers have signal swings equivalent to that of standard PECL
drivers, and are capable of driving AC-coupled optical
modules or transmission lines.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Note. When a disabled channel (i.e., both outputs disabled) is
re-enabled:
Device Configuration and Control Interface
The CYV15G0403TB is highly configurable via the configu-
ration interface. This interface allows the device to be
configured globally or allows each channel to be configured
independently. Table 2 lists the configuration latches within the
device including the initialization value of the latches upon the
assertion of RESET. Table 3 shows how the latches are
mapped in the device. Each row in the Table 3 maps to a 5-bit
latch bank. There are 16 such write-only latch banks. When
WREN = 0, the logic value in DATA[4:0] is latched to the latch
bank specified by the values in ADDR[3:0]. The second
column of Table 3 specifies the channels associated with the
corresponding latch bank. For example, the first three latch
banks (0,1 and 2) consist of configuration bits for channel A.
The latch banks 12, 13 and 14 consist of Global configuration
bits and the last latch bank (15) is the Mask latch bank that can
be configured to perform bit-by-bit configuration.
Global Enable Function
The global enable function, controlled by the GLENx bits, is a
feature that can be used to reduce the number of write opera-
tions needed to setup the latch banks. This function is
beneficial in systems that use a common configuration in
multiple channels. The GLENx bit is present in bit 0 of latch
banks 0 through 11 only. Its default value (1) enables the global
• data on the serial outputs may not meet all timing specifi-
• the state of the phase-align buffer cannot be guaranteed,
cations for up to 250 µs
and a phase-align reset is required if the phase-align buffer
is used
update of the latch bank's contents. Setting the GLENx bit to
0 disables this functionality.
Latch Banks 12, 13, and 14 are used to load values in the
related latch banks in a global manner. A write operation to
latch bank 12 could do a global write to latch banks 0, 3, 6, and
9 depending on the value of GLENx in these latch banks; latch
bank 13 could do a global write to latch banks 1, 4, 7 and 10;
and latch banks 14 could do a global write to latch banks 2, 5,
8 and 11. The GLENx bit cannot be modified by a global write
operation.
Force Global Enable Function
FGLENx forces the global update of the target latch banks, but
does not change the contents of the GLENx bits. If FGLENx =
1 for the associated global channel, FGLENx forces the global
update of the target latch banks.
Mask Function
An additional latch bank (15) is used as a global mask vector
to control the update of the configuration latch banks on a bit-
by-bit basis. A logic 1 in a bit location allows for the update of
that same location of the target latch bank(s), whereas a logic
0 disables it. The reset value of this latch bank is FFh, thereby
making its use optional by default. The mask latch bank is not
maskable. The FGLEN functionality is not affected by the bit 0
value of the mask latch bank.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
0, 1, 3, 4, 6, 7, 9, and 10) are the static control latches. The
third row of latches for each channel (address numbers 2, 5,
8, and 11) are the dynamic control latches that are associated
with enabling dynamic functions within the device.
Latch Bank 14 is also useful for those users that do not need
the latch-based programmable feature of the device. This
latch bank could be used in those applications that do not need
to modify the default value of the static latch banks, and that
can afford a global (i.e., not independent) control of the
dynamic signals. In this case, this feature becomes available
when ADDR[3:0] is left unchanged with a value of “1110” and
WREN is left asserted. The signals present in DATA[4:0] effec-
tively become global control pins, and for the latch banks 2, 5,
8 and 11.
Static Latch Values
There are some latches in the table that have a static value
(i.e. 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be
configured with their corresponding value each time that their
associated latch bank is configured. The latches that have an
‘X’ are don’t cares and can be configured with any value.
CYV15G0403TB
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