cyv15g0403tb Cypress Semiconductor Corporation., cyv15g0403tb Datasheet - Page 9

• Manufacturer Part Number: cyv15g0403tb
• Description: Independent Clock Quad Hotlink Ii Serializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02104 Rev. *B
Pin Definitions
CYV15G0403TB Quad HOTLink II Serializer
CYV15G0403TB HOTLink II Operation
The CYV15G0403TB is a highly configurable, independent
clocking, quad-channel serializer designed to support reliable
transfer of large quantities of digital video data, using high-
speed serial links from multiple sources to multiple destina-
tions. This device supports four 10-bit channels.
CYV15G0403TB Transmit Data Path
Input Register
The parallel input bus TXDx[9:0] can be clocked in using
TXCLKx (TXCKSELx = 0) or REFCLKx (TXCKSELx = 1).
Phase-Align Buffer
Data from each Input Register is passed to the associated
Phase-Align Buffer, when the TXDx[9:0] input registers are
clocked using TXCLKx (TXCKSELx = 0 and TXRATEx = 0).
When the TXDx[9:0] input registers are clocked using
REFCLKx± (TXCKSELx = 1) and REFCLKx± is a full-rate
clock, the associated Phase Alignment Buffer in the transmit
path is bypassed. These buffers are used to absorb clock
phase differences between the TXCLKx input clock and the
internal character clock for that channel.
Once initialized, TXCLKx is allowed to drift in phase as much
as ±180 degrees. If the input phase of TXCLKx drifts beyond
the handling capacity of the Phase Align Buffer, TXERRx is
asserted to indicate the loss of data, and remains asserted
until the Phase Align Buffer is initialized. The phase of the
TXCLKx relative to its associated internal character rate clock
is initialized when the configuration latch PABRSTx is written
as 0. When the associated TXERRx is deasserted, the Phase
Align Buffer is initialized and input characters are correctly
captured.
If the phase offset, between the initialized location of the input
clock and REFCLKx, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on that
channel’s TXERRx output. This output indicates an error
continuously until the Phase-Align Buffer for that channel is
reset. While the error remains active, the transmitter for that
channel outputs a continuous “1001111000” character (LSB
first) to indicate to the remote receiver that an error condition
is present in the link.
Transmit BIST
Each channel contains an internal pattern generator that can
be used to validate both the link and device operation. These
generators are enabled by the associated TXBISTx latch via
the device configuration interface. When enabled, a register in
the associated channel becomes a signature pattern
generator by logically converting to a Linear Feedback Shift
Register (LFSR). This LFSR generates a 511-character
TRST
V
GND
Name
Power
CC
LVTTL Input,
internal pull-up
I/O Characteristics Signal Description
(continued)
JTAG reset signal. When asserted (LOW), this input asynchronously resets the JTAG
test access port controller.
+3.3V Power.
Signal and Power Ground for all internal circuits.
sequence. This provides a predictable yet pseudo-random
sequence that can be matched to an identical LFSR in the
attached Receiver(s).
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
All data present at the associated TXDx[9:0] inputs are ignored
when BIST is active on that channel.
Transmit PLL Clock Multiplier
Each Transmit PLL Clock Multiplier accepts a character-rate
or half-character-rate external clock at the associated
REFCLKx± input, and that clock is multiplied by 10 or 20 (as
selected by TXRATEx) to generate a bit-rate clock for use by
the transmit shifter. It also provides a character-rate clock used
by the transmit paths, and outputs this character rate clock as
TXCLKOx.
Each clock multiplier PLL can accept a REFCLKx± input
between 19.5 MHz and 150 MHz, however, this clock range is
limited by the operating mode of the CYV15G0403TB clock
multiplier (TXRATEx) and by the level on the associated
SPDSELx input.
SPDSELx are 3-level select
operating ranges for the serial data outputs and inputs of the
associated channel. The operating serial signaling-rate and
allowable range of REFCLKx± frequencies are listed in
Table 1.
Table 1. Operating Speed Settings
The REFCLKx± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKx+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
the true or complement REFCLKx input, and leave the
alternate REFCLKx input open (floating).
When both the REFCLKx+ and REFCLKx– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC-or AC-
coupled or a differential LVTTL or LVCMOS clock.
MID (Open)
SPDSELx
HIGH
LOW
TXRATEx
1
0
1
0
1
0
[4]
inputs that select one of three
REFCLKx±
Frequency
reserved
19.5–40
80–150
CYV15G0403TB
(MHz)
20–40
40–80
40–75
Rate (Mbps)
Page 9 of 21
Signaling
800–1500
195–400
400–800
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