cyv15g0104trb Cypress Semiconductor Corporation., cyv15g0104trb Datasheet
cyv15g0104trb
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cyv15g0104trb Summary of contents
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... CYV15G0104TRB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices. The transmit (TX) channel of the CYV15G0104TRB HOTLink II device accepts scrambled 10-bit transmission characters. These characters are serialized and output from ...
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... The CYV15G0104TRB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi- CYV15G0104TRB Serializer and Reclocking Deserializer Logic Block Diagram Document #: 38-02100 Rev. *B format routers, switchers, format converters, SDI monitors, cameras, and camera control units ...
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... Clock Multiplier Clock Multiplier Character-Rate Clock TXBISTB PABRSTB RXRATEA RXPLLPDA TRGRATEA TXRATEB TXCKSELB PABRSTB SDASEL[2..1]A[1:0] TOE[2..1]B ROE[2..1]A RXBISTA[1:0] TXBISTB CYV15G0104TRB RESET TRST JTAG TMS Boundary TCLK Scan TDI Controller TDO LFIA 10 RXDA[9:0] 10 BISTSTA ÷2 RXCLKA+ RXCLKA– ROE[2..1]A ROUTA1+ ROUTA1– ...
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... CLKB– REF RE NC GND NC GND GND CLKB+ CLKOA ADDR ADDR RX REPDO NC GND GND [2] [1] CLKA GND NC GND GND CLKOB CLKA– CYV15G0104TRB ROUT A2– A2– IN ROUT A2+ A2+ ...
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... RE REF GND GND GND NC GND CLKOA CLKB+ REPDO RX ADDR ADDR GND GND GND A CLKA+ [1] [ GND GND GND NC GND CLKA– CLKOB CYV15G0104TRB TOUT B1– TOUT B1+ TMS ...
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... Pin Definitions CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDB[9:0] LVTTL Input, Transmit Data Inputs. TXDB[9:0] data inputs are captured on the rising edge of the synchronous, transmit interface clock. The transmit interface clock is selected by the TXCKSELB latch sampled by via the device configuration interface ...
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... Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description BISTSTA LVTTL Output, BIST Status Output. When RXBISTA[1:0] = 10, BISTSTA (along with RXDA[1:0]) synchronous to the displays the status of the BIST reception. See Table 6 for the BIST status reported for RXCLKA ± ...
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... Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description [4] SPDSELA 3-Level Select Serial Rate Select. The SPDSELA and SPDSELB inputs specify the operating signaling- SPDSELB static control input rate range of the receive and transmit PLL, respectively. LOW = 195 – 400 MBd MID = 400 – ...
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... Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description [6] ROE2A Internal Latch Reclocker Differential Serial Output Driver 2 Enable. [6] ROE1A Internal Latch Reclocker Differential Serial Output Driver 1 Enable. [6] PABRSTB Internal Latch Transmit Clock Phase Alignment Buffer Reset. Factory Test Modes ...
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... TXCLKOB. The clock multiplier PLL can accept a REFCLKB± input between 19.5 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYV15G0104TRB clock multiplier (TXRATEB) and by the level on the SPDSELB input. [4] ...
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... Clock/Data Recovery The extraction of a bit-rate clock and recovery of bits from the received serial stream is performed by a separate CDR block within the receive channel. The clock extraction function is CYV15G0104TRB TRGCLKA± Frequency Signaling (MHz) ...
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... WAIT_FOR_BIST state where it monitors the receive path for the first character of the next BIST sequence. Power Control The CYV15G0104TRB supports user control of the powered up or down state of each transmit and receive channel. The receive channels are controlled by the RXPLLPDA latch via ...
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... Device Reset State When the CYV15G0104TRB is reset by assertion of RESET, all state machines, counters, and configuration latches in the device are initialized to a reset state. See Table 4 for the initialize values of the configuration latches. ...
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... TXCLKB input clock relative to REFCLKB+/- is initialized. PABRSTB is an asynchronous input, but is sampled by each TXCLKB↑ to synchronize it to the internal clock domain. PABRSTB is a self clearing latch. This eliminates the requirement of writing complete the initialization of the Phase Alignment Buffer. Document #: 38-02100 Rev. *B CYV15G0104TRB Page [+] Feedback ...
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... X TXBISTB JTAG Support The CYV15G0104TRB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan, and bypass are supported. This capability is present only on the LVTTL inputs and outputs, the TRGCLKA± input, and the REFCLKB± clock input. The high- speed serial inputs and outputs are not part of the JTAG test chain ...
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... BIST_START (101) Start of BIST Detected Compare Next Character Match End-of-BIST State Yes, {BISTSTA, RXDA[0], RXDA[1]} = BIST_LAST_GOOD (010) BIST_ERROR (110) Figure 2. Receive BIST State Machine CYV15G0104TRB Receive BIST Detected LOW RX PLL Out of Lock {BISTSTA, RXDA[0], RXDA[1]} = BIST_DATA_COMPARE (000, 001) No Page [+] Feedback ...
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... Document #: 38-02100 Rev. *B Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYV15G0104TRB requires one power supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Operating Range + 0.5V CC ...
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... LVTTL Output Test Load 3.0V 2.0V 2. 1.4V th 0.8V 0.8V GND ≤ (c) LVTTL Input Test Waveform CYV15G0104TRB AC Electrical Characteristics Parameter CYV15G0104TRB Transmitter LVTTL Switching Characteristics Over the Operating Range f TXCLKB Clock Cycle Frequency TS t TXCLKB Period=1/f TXCLK [16] t TXCLKB HIGH Time TXCLKH [16] t TXCLKB LOW Time ...
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... TXCLKOB Clock Frequency = REFCLKB Frequency TOS t TXCLKOB Period=1/f TXCLKO t TXCLKOB Duty Cycle centered at 60% HIGH time TXCLKOD CYV15G0104TRB Receiver LVTTL Switching Characteristics Over the Operating Range f RXCLKA± Clock Output Frequency RS t RXCLKA± Period = 1/f RXCLKP t RXCLKA± Duty Cycle Centered at 50% (Full Rate and Half Rate) ...
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... JTAG Test Clock Period TCLK CYV15G0104TRB Device RESET Characteristics Over the Operating Range t Device RESET Pulse Width RST CYV15G0104TRB Transmitter and Reclocker Serial Output Characteristics Over the Operating Range Parameter t Bit Time B [16] t CML Output Rise Time 20−80% (CML Test Load) ...
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... PLL Characteristics Parameter Description CYV15G0104TRB Receive PLL Characteristics Over the Operating Range t Receive PLL lock to input data stream (cold start) RXLOCK Receive PLL lock to input data stream t Receive PLL Unlock Rate RXUNLOCK [16] Capacitance Parameter Description C TTL Input Capacitance INTTL C PECL input Capacitance ...
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... Transmit Interface TXCLKOB Timing t TXRATEB = 0 REFCLKB Note29 TXCLKOB Switching Waveforms for the CYV15G0104TRB HOTLink II Receiver Receive Interface Read Timing RXRATEA = 0 RXCLKA+ RXCLKA– RXDA[9:0] Notes: 28. The TXCLKOB output remains at the character rate regardless of the state of TXRATEB and does not follow the duty cycle of REFCLKB±. ...
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... Switching Waveforms for the CYV15G0104TRB HOTLink II Receiver Receive Interface Read Timing RXRATEA = 1 RXCLKA+ RXCLKA– RXDA[9:0] Bus Configuration Write Timing ADDR[2:0] DATA[6:0] WREN Document #: 38-02100 Rev RXCLKP t RXDV– t RXDV+ t WRENP t DATAS CYV15G0104TRB t DATAH Page [+] Feedback ...
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... VCC POWER E04 VCC POWER E17 VCC POWER E18 VCC POWER E19 VCC POWER E20 VCC POWER F01 NC NO CONNECT CYV15G0104TRB Ball ID Signal Name Signal Type F17 VCC POWER F18 NC NO CONNECT F19 NC NO CONNECT F20 NC NO CONNECT G01 GND GROUND ...
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... V17 RXDA[9] LVTTL OUT V18 RXDA[5] LVTTL OUT V19 RXDA[2] LVTTL OUT V20 RXDA[1] LVTTL OUT W01 TXDB[5] LVTTL IN W02 TXDB[7] LVTTL IN CYV15G0104TRB Ball ID Signal Name Signal Type L20 GND GROUND M01 NC NO CONNECT M02 NC NO CONNECT W03 NC NO CONNECT W04 ...
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... HOTLink is a registered trademark and HOTLink trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-02100 Rev. *B Package Name Package Type BL256 256-Ball Thermally Enhanced Ball Grid Array BL256 Pb-Free 256-Ball Thermally Enhanced Ball Grid Array CYV15G0104TRB Operating Range Commercial Commercial 51-85123-*E Page [+] Feedback ...
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... Document History Page Document Title: CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer Document Number: 38-02100 ISSUE REV. ECN NO. DATE ** 244348 See ECN *A 338721 See ECN *B 384307 See ECN Document #: 38-02100 Rev. *B ORIG. OF CHANGE DESCRIPTION OF CHANGE FRE New Data Sheet ...