cyv15g0104trb Cypress Semiconductor Corporation., cyv15g0104trb Datasheet - Page 15

• Manufacturer Part Number: cyv15g0104trb
• Description: Independent Clock Hotlink Ii Serializer And Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02100 Rev. *B
Table 5. Device Control Latch Configuration Table
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
Table 6. Receive BIST Status Bits
1. Pulse RESET Low after device power-up. This operation
2. Set the static latch banks for the target channel.
3. Set the dynamic bank of latches for the target channel.
4. Reset the Phase Alignment Buffer. [Optional if phase align
{BISTSTA, RXDA[0], RXDA[1]}
ADDR
(000b)
(001b)
(010b)
(100b)
(101b)
(011b)
(110b)
(111b)
resets both channels.
Enable the Receive PLL and/or transmit channel. If the
receiver is enabled, set the device for SMPTE data
reception (RXBISTA[1:0] = 01) or BIST data reception
(RXBISTA[1:0] = 10).
buffer is bypassed.]
0
1
2
3
4
5
6
7
Channel Type
A
A
A
B
B
B
000, 001
010
011
100
101
110
111
S
S
D
S
S
D
SDASEL2A[1]
RXBISTA[1]
DATA6
1
X
X
X
BIST Data Compare. Character compared correctly.
BIST Last Good. Last Character of BIST sequence detected and valid.
Reserved.
BIST Last Bad. Last Character of BIST sequence detected invalid.
BIST Start. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock condition.
BIST Error. While comparing characters, a mismatch was found in one or more of the
character bits.
BIST Wait. The receiver is comparing characters but has not yet found the start of BIST
character to enable the LFSR.
SDASEL2A[0]
RXPLLPDA
DATA5
0
X
X
0
SDASEL1A[1]
RXBISTA[0]
DATA4
X
X
X
X
DO NOT WRITE TO THESE ADDRESSES
INTERNAL TEST REGISTERS
JTAG Support
The CYV15G0104TRB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs, the
TRGCLKA± input, and the REFCLKB± clock input. The high-
speed serial inputs and outputs are not part of the JTAG test
chain.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0104TRB is ‘0C811069’x.
(Receive BIST = Enabled)
SDASEL1A[0]
TXBISTB
Receive BIST Status
DATA3
X
X
X
X
Description
ROE2A
TOE2B
DATA2
X
0
X
0
TXCKSELB
ROE1A
TOE1B
DATA1
CYV15G0104TRB
X
0
0
TRGRATEA
RXRATEA
TXRATEB
PABRSTB
DATA0
X
X
Page 15 of 27
1010110
1011001
1010110
1011001
1011111
1011111
Reset
Value
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