cyv15g0104trb Cypress Semiconductor Corporation., cyv15g0104trb Datasheet - Page 8

• Manufacturer Part Number: cyv15g0104trb
• Description: Independent Clock Hotlink Ii Serializer And Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02100 Rev. *B
Pin Definitions
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer
SPDSELA
SPDSELB
INSELA
LFIA
WREN
ADDR[2:0]
DATA[6:0]
RXRATEA
SDASEL[2..1]
A[1:0]
TXCKSELB
TXRATEB
TRGRATEA
RXPLLPDA
RXBISTA[1:0] Internal Latch
TXBISTB
TOE2B
TOE1B
Notes:
4.
5.
6.
Name
Device Configuration and Control Bus Signals
Internal Device Configuration Latches
3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to V
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface.
See Device Configuration and Control Interface for detailed information on the internal latches.
3-Level Select
static control input
LVTTL Input,
asynchronous
LVTTL Output,
asynchronous
LVTTL input,
asynchronous,
internal pull-up
LVTTL input
asynchronous,
internal pull-up
LVTTL input
asynchronous,
internal pull-up
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
I/O Characteristics
(continued)
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[6]
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[6]
[6]
[6]
[6]
[6]
[6]
[4]
SS
(ground). The HIGH level is usually implemented by direct connection to V
Serial Rate Select. The SPDSELA and SPDSELB inputs specify the operating signaling-
rate range of the receive and transmit PLL, respectively.
LOW = 195 – 400 MBd
MID = 400 – 800 MBd
HIGH = 800 – 1500 MBd.
Receive Input Selector. The INSELA input determines which external serial bit stream
is passed to the receiver’s Clock and Data Recovery circuit. When INSELA is HIGH, the
Primary Differential Serial Data Input, INA1±, is selected for the receive channel. When
INSELA is LOW, the Secondary Differential Serial Data Input, INA2±, is selected for the
receive channel.
Link Fault Indication Output. LFIA is an output status indicator signal. LFIA is the logical
OR of six internal conditions. LFIA is asserted LOW when any of the following conditions
is true:
Control Write Enable. The WREN input writes the values of the DATA[6:0] bus into the
latch specified by the address location on the ADDR[2:0] bus.
Control Addressing Bus. The ADDR[2:0] bus is the input address bus used to configure
the device. The WREN input writes the values of the DATA[6:0] bus into the latch specified
by the address location on the ADDR[2:0] bus.
within the device, and the initialization value of the latches upon the assertion of RESET.
Table 5 shows how the latches are mapped in the device.
Control Data Bus. The DATA[6:0] bus is the input data bus used to configure the device.
The WREN input writes the values of the DATA[6:0] bus into the latch specified by address
location on the ADDR[2:0] bus.
and the initialization value of the latches upon the assertion of RESET. Table 5 shows how
the latches are mapped in the device.
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Transmit Clock Select.
Transmit PLL Clock Rate Select.
Reclocker Output PLL Clock Rate Select.
Receive Channel Power Control.
Receive Bist Disabled.
Transmit Bist Disabled.
Transmitter Differential Serial Output Driver 2 Enable.
Transmitter Differential Serial Output Driver 1 Enable.
Signal Description
• Received serial data rate outside expected range
• Analog amplitude below expected levels
• Transition density lower than expected
• Receive channel disabled
• ULCA is LOW
• Absence of TRGCLKA±.
[5 ]
Table 4 lists the configuration latches within the device,
[5]
Table 4 lists the configuration latches
CC
CYV15G0104TRB
(power). The MID level is usually
[5]
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