cyv15g0104trb Cypress Semiconductor Corporation., cyv15g0104trb Datasheet - Page 9

• Manufacturer Part Number: cyv15g0104trb
• Description: Independent Clock Hotlink Ii Serializer And Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02100 Rev. *B
Pin Definitions
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer
CYV15G0104TRB HOTLink II Operation
The CYV15G0104TRB is a highly configurable, independent
clocking device designed to support reliable transfer of large
quantities of digital video data, using high-speed serial links
from multiple sources to multiple destinations.
ROE2A
ROE1A
PABRSTB
SCANEN2
TMEN3
TOUTB1±
TOUTB2±
ROUTA1±
ROUTA2±
INA1±
INA2±
TMS
TCLK
TDO
TDI
TRST
V
GND
Name
Factory Test Modes
Analog I/O
JTAG Interface
Power
CC
Internal Latch
Internal Latch
Internal Latch
LVTTL input,
internal pull-down
LVTTL input,
internal pull-down
CML Differential
Output
CML Differential
Output
CML Differential
Output
CML Differential
Output
Differential Input
Differential Input
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-down
3-State LVTTL Output Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected.
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-up
I/O Characteristics
(continued)
[6]
[6]
[6]
Reclocker Differential Serial Output Driver 2 Enable.
Reclocker Differential Serial Output Driver 1 Enable.
Transmit Clock Phase Alignment Buffer Reset.
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as a NO
CONNECT, or GND only.
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a NO
CONNECT, or GND only.
Transmitter Primary Differential Serial Data Output. The transmitter TOUTB1± PECL-
compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
Transmitter Secondary Differential Serial Data Output. The transmitter TOUTB2± PECL-
compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines
or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
Reclocker Primary Differential Serial Data Output. The reclocker ROUTA1± PECL-
compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
Reclocker Secondary Differential Serial Data Output. The reclocker ROUTA2± PECL-
compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines
or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
Primary Differential Serial Data Input. The INA1± input accepts the serial data stream
for deserialization. The INA1± serial stream is passed to the receive CDR circuit to extract
the data content when INSELA = HIGH.
Secondary Differential Serial Data Input. The INA2± input accepts the serial data
stream for deserialization. The INA2± serial stream is passed to the receiver CDR circuit
to extract the data content when INSELA = LOW.
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high for
≥5 TCLK cycles, the JTAG test controller is reset.
JTAG Test Clock.
Test Data In. JTAG data input port.
JTAG reset signal. When asserted (LOW), this input asynchronously resets the JTAG
test access port controller.
+3.3V Power.
Signal and Power Ground for all internal circuits.
Signal Description
CYV15G0104TRB Transmit Data Path
Input Register
The parallel input bus TXDB[9:0] can be clocked in using
TXCLKB (TXCKSELB = 0) or REFCLKB (TXCKSELB = 1).
CYV15G0104TRB
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