cyv15g0104trb Cypress Semiconductor Corporation., cyv15g0104trb Datasheet - Page 19

• Manufacturer Part Number: cyv15g0104trb
• Description: Independent Clock Hotlink Ii Serializer And Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02100 Rev. *B
CYV15G0104TRB AC Electrical Characteristics
t
t
t
t
f
t
t
CYV15G0104TRB Receiver LVTTL Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
f
t
t
CYV15G0104TRB REFCLKB Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
t
t
CYV15G0104TRB TRGCLKA Switching Characteristics Over the Operating Range
f
t
Notes:
17. The ratio of rise time to falling time must not vary by greater than 2:1.
18. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
19. All transmit AC timing parameters measured with 1ns typical rise time and fall time.
20. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
21. Receiver UI (Unit Interval) is calculated as 1/(f
22. The duty cycle specification is a simultaneous condition with the t
TXCLKR
TXCLKF
TXDS
TXDH
TOS
TXCLKO
TXCLKOD
RS
RXCLKP
RXCLKD
RXCLKR
RXCLKF
RXDv–
RXDv+
ROS
RECLKO
RECLKOD
REF
REFCLK
REFH
REFL
REFD
REFR
REFF
TREFDS
TREFDH
TRG
REFCLK
Parameter
cycle cannot be as large as 30%–70%.
[16, 17, 18, 19]
[22]
[16, 17, 18, 19]
[20]
[20]
[16, 17, 18, 19]
[16, 17, 18, 19]
[16]
[16]
TXCLKB Rise Time
TXCLKB Fall Time
Transmit Data Set-up Time to TXCLKB↑ (TXCKSELB = 0)
Transmit Data Hold Time from TXCLKB↑ (TXCKSELB = 0)
TXCLKOB Clock Frequency = 1x or 2x REFCLKB Frequency
TXCLKOB Period=1/f
TXCLKOB Duty Cycle centered at 60% HIGH time
RXCLKA± Clock Output Frequency
RXCLKA± Period = 1/f
RXCLKA± Duty Cycle Centered at 50% (Full Rate and Half Rate)
RXCLKA± Rise Time
RXCLKA± Fall Time
Status and Data Valid Time to RXCLKA± (RXRATEA = 0) (Full Rate)
Status and Data Valid Time to RXCLKA± (RXRATEA = 1) (Half Rate)
Status and Data Valid Time to RXCLKA± (RXRATEA = 0)
Status and Data Valid Time to RXCLKA± (RXRATEA = 1)
RECLKOA Clock Frequency
RECLKOA Period=1/f
RECLKOA Duty Cycle centered at 60% HIGH time
REFCLKB Clock Frequency
REFCLKB Period = 1/f
REFCLKB HIGH Time (TXRATEB = 1)(Half Rate)
REFCLKB HIGH Time (TXRATEB = 0)(Full Rate)
REFCLKB LOW Time (TXRATEB = 1)(Half Rate)
REFCLKB LOW Time (TXRATEB = 0)(Full Rate)
REFCLKB Duty Cycle
REFCLKB Rise Time (20%–80%)
REFCLKB Fall Time (20%–80%)
Transmit Data Set-up Time to REFCLKB - Full Rate
(TXRATEB = 0, TXCKSELB = 1)
Transmit Data Set-up Time to REFCLKB - Half Rate
(TXRATEB = 1, TXCKSELB = 1)
Transmit Data Hold Time from REFCLKB - Full Rate
(TXRATEB= 0, TXCKSELB = 1)
Transmit Data Hold Time from REFCLKB - Half Rate
(TXRATEB = 1, TXCKSELB = 1)
TRGCLKA Clock Frequency
TRGCLKA Period = 1/f
TRG
TOS
ROS
* 20) (when TRGRATEA = 1) or 1/(f
RS
REF
TRG
Description
REFH
and t
(continued)
REFL
TRG
parameters. This means that at faster character rates the REFCLKB± duty
* 10) (when TRGRATEA = 0). In an operating link this is equivalent to t
5UI–2.0
5UI–1.3
5UI–1.8
5UI–2.6
2.9
2.9
CYV15G0104TRB
Min.
19.5
6.66
–1.9
9.75
6.66
–1.0
19.5
6.66
19.5
19.5
-1.9
0.2
0.3
0.3
0.2
2.2
1.0
6.6
5.9
5.9
2.4
2.3
1.0
1.6
6.6
30
[16]
[16]
[21]
[21]
[21]
[21]
102.56
51.28
51.28
51.28
51.28
Max
+1.0
150
150
150
150
150
1.7
1.7
1.2
1.2
70
0
0
2
2
Page 19 of 27
MHz
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
B
.
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