ncn6004a ON Semiconductor, ncn6004a Datasheet - Page 38

• Manufacturer Part Number: ncn6004a
• Description: Dual Sam/sim Interface Integrated Circuit
• Manufacturer: ON Semiconductor

PIN FUNCTIONS AND DESCRIPTION
POWER SUPPLY SECTION
DIGITAL INPUT SECTION @ 2.70 < V
Normal Operating Mode
CARD INTERFACE SECTION @ 2.70 < V
Normal Operating Mode
DIGITAL DYNAMIC SECTION NORMAL OPERATING
MODE
DIGITAL DYNAMIC SECTION PROGRAMMING MODE
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PROGRAMMING AND STATUS FUNCTIONS
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SYSTEM STATES UPON START UP
PARALLEL/MULTIPLEXED OPERATION MODES
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CARD POWER SUPPLY TIMING
POWER DOWN OPERATION
CARD DETECTION
POWER MANAGEMENT
OUTPUT VOLTAGE PROGRAMMING
DC/DC CONVERTER
CLOCK DIVIDER
PARALLEL OPERATION
DATA I/O LEVEL SHIFTER
ESD PROTECTION
SECURITY FEATURES
TEST BOARD SCHEMATIC DIAGRAM
Figures
Figure 1: Pin Diagram
Figure 2: Typical Applications
Figure 3: Block Diagram
Figure 4: Programming Sequence
Figure 5: Reading ANLG_VCC Status
Figure 6: Simplified MUX_MODE Logic and
Multiplex CIrcuit
Figure 7: Card Power Supply Turn ON and
Shut OFF Typical Sequence
Figure 8: Card Power Down Sequence
Figure 9: Power Down Sequence
Figure 10: Power Down Sequence: Timing Details
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Figure 11: Typical Interrupt Sequence
Figure 12: Card Power Supply Controls
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Figure 13: Power On Sequence Timing
Figure 14: Power On and CARD_SEL Sequence
Timings
Figure 15: Basic DC/DC Converter Diagram
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Figure 16: Theoretical DC/DC Operating
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CC
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< 5.50V,
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CC
< 5.50V,
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10
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2
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3
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http://onsemi.com
NCN6004A
38
Figure 17: Typical CRD_VCC Ripple Voltage
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Figure 18: Typical Card Voltage Turn ON and Start−up
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Figure 19: Typical Card Supply Turn OFF
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Figure 20: CRD_VCC Efficiency as a Function of the
Input Supply Voltage
Figure 21: Typical Output Voltage Ripple
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Figure 22: Output Current Limit
Figure 23: Output Current Limit as a Function of the
Temperature
Figure 24: Simplified Frequency Divider and
Programming Functions
Figure 25: Clock Programming Timings
Figure 26: Card Clock ½ Divider Operation
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Figure 27: Clock Divider: 8 to 1 Operation
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Figure 28: Clock Divider Timing Details
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Figure 29: Clock Divider: Run to Stop High Operation
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Figure 29: Typical Rise and Fall Time in Fast and Slow
Operating Mode
Figure 30: Parallel Operation Wiring "
MUX_MODE = High
Figure 31: Multiplexed Operation Wiring "
MUX_MODE = Low
Figure 32: Dual Bi−directional I/O line Level Shifter
and Multiplex
Figure 33: Typical I/O Rise and Fall Time
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Figure 34: Test Board Schematic Diagram
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Figure 35: Demo Board PCB Top Overlay
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Figure 37: Demo Board PCB Top Layer
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Figure 38: Demo Board PCB Bottom Layer
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Table 1 :Programming and Reading Basic Functions
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Table 2: Programming Functions
Table 3: Status Pins Data
Table 4: Operating Conditions Upon Start−up
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Table 5: Card Detection Polarity
Table 6: Ceramic/Electrolytic Capacitors Comparison
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Table 7: Programming Clock Routing
Table 8: Output Clock Slope Selection
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