ncn6004a ON Semiconductor, ncn6004a Datasheet - Page 8

• Manufacturer Part Number: ncn6004a
• Description: Dual Sam/sim Interface Integrated Circuit
• Manufacturer: ON Semiconductor

PIN DESCRIPTION (continued)
Pin
39
40
41
42
43
44
45
46
CRD_DET_B
MUX_MODE
ANLG_GND
ANLG_VCC
CRD_C4_B
CRD_C8_B
EN_RPU
STATUS
Symbol
GROUND
OUTPUT
OUTPUT
OUTPUT
POWER
INPUT
INPUT
INPUT
Type
This pin controls the card #B C4 contact, according to the ISO specification. A built−in level
shifter is used to adapt the card and the MCU, regardless of the power supply voltage of
each signals. The signal present at this pin is latched upon either CARD_SEL or CS or
PGM positive going transient and resume to a transparent mode when card #B is selected.
The pin is hardwired to zero, the bias being provided by the V
V
This pin controls the card #B C8 contact, according to the ISO specification. A built−in
level shifter is used to adapt the card and the MCU, regardless of the power supply
voltage of each signals. The signal present at this pin is latched upon either CARD_SEL
or CS or PGM positive going transient and resume to a transparent mode when card #B
is selected.
The pin is hardwired to zero, the bias being provided by the V
V
This pin senses the signal coming from the external smart card connector to detect the
presence of card #B. The polarity of the signal is programmable as Normally Open or
Normally Close switch. The logic signal will be activated when the level is either Low or
High, with respect to the polarity defined previously. By default, the input is Normally
Open. A built−in circuit prevents uncontrolled short pulses to generate an INT signal. The
digital filter eliminates pulse width below 50 ms.
This pin is connected to the positive external power supply. The device sustains any
voltage from +2.7 V to +5.5 V. This voltage supplies the NCN6004A internal Analog and
Logic circuits. A high quality capacitor must be connected across this pin and
ANLG_GND, 10 mF/6 V is recommended. A set of extra pins (28 and 33) are provided to
connect the power supply to the internal DC/DC converter.
Note: The voltage present at pin 28 and 33 must be equal to the voltage present at pin 42
This pin is the ground reference for both analog and digital signals and must be
connected to the system Ground. Care must be observed to provide a copper PCB layout
designed to avoid small signals and power transients sharing the same track. Good high
frequency techniques are strongly recommended.
This pin selects the mode of operation of the card signals from the MPU side. When
MUX_MODE = Low, all the card signals are fully de−multiplexed and data transfers can
take place with both cards simultaneously. On top of that, both cards can be accessed
during the programming sequence, assuming the external microcontroller is capable to
run multi tasks software.
When MUX_MODE = High, all the card signals are multiplexed and the communications
with the cards shall take place in a sequential mode. The card is selected by setting
CARD_SEL high or Low. The internal logic will disable the CARD_B inputs and use
CARD_SEL inputs as a single channel to controls both output smart cards sequentially
when MUX_MODE = H.
Moreover, when MUX_MODE = High, all the B channel mP dedicated pins, except
CLOCK_IN_B, pin 15, are forced to a high level by means of internal pull up resistors. It
is not necessary to connect these pins (16, 17, 18 and 19) to an external bias voltage, but
it is mandatory to avoid any connections to ground. On the other hand, in this case the
internal pull up resistor connected across I/O_A, pin 9 and V
disconnected to avoid a current overload on the I/O line.
This pin provides a logic input to valid or not the internal pullup resistors connected
across each I/O, RESET, C4 and C8 lines and ANLG_VCC.
When EN_RPU = High, the pull up resistors are connected
When EN_RPU = Low, the pull up resistors are disconnected and it is up to the designer
to set up the external resistor to cope with the ISO/EMV specifications.
The logic signal must be set up prior to apply the ANLG_VCC supply. Once the logic
mode has been acknowledged by the internal Power On reset, it cannot be changed until
a new startup sequence is launched.
This pin provides a logic state related to the card [A or B] insertion, the VCC_OK, the
CRD_VCC value and the current overflow powered to either card [A or B]. The internal
register can be read when PGM = High. The logic level is forced to High when the input
voltage drops below the V
the STATUS pin is not pulled down externally.
The associated pullup resistor is either connected to V
when EN_RPU = Low.
CC
CC
voltage drops below 2.7 V, or during the CRD_VCC_B startup time.
voltage drops below 2.7 V, or during the CRD_VCC_B startup time.
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NCN6004A
8
bat
min (2.0 V), thus reducing the stand by current, assuming
Description
CC
(EN_RPU = H) or disconnected
CC
CC
CC
is automatically
supply, when either the
supply, when either the