ncn6004a ON Semiconductor, ncn6004a Datasheet - Page 5

• Manufacturer Part Number: ncn6004a
• Description: Dual Sam/sim Interface Integrated Circuit
• Manufacturer: ON Semiconductor

PIN DESCRIPTION (continued)
Pin
10
12
13
14
15
16
17
11
CLOCK_IN_A
CLOCK_IN_B
ANLG_GND
RESET_A
Symbol
C4_A
C8_A
C8_B
C4_B
High Impedance
High Impedance
Clock Input,
Clock Input,
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
Type
The signal present on this pin is translated to the RST pin of the external smart card #A. The
CS signal must be Low to validate the RESET function, regardless of the selected card.
Assuming the mP provides two independent lines to control the RESET pins, the
NCN6004A can control two cards simultaneously.
When MUX_MODE = High, this pin provides an access to either card A or B Reset by
means of CARD_SEL selection bit.
The associated pull up resistor is either connected to V
disconnected when EN_RPU = Low.
This pin controls the card #A C4 contact The signal can be either de−multiplexed, at MPU
level, or is multiplexed with C4_B, depending upon the MUX_MODE logic state.
When MUX_MODE = High, this pin provides an access to either card A or B C4 channel
by means of CARD_SEL selection bit.
The associated pull up resistor is either connected to V
disconnected when EN_RPU = Low.
This pin controls the card #A C8 contact. The signal can be either de−multiplexed, at MPU
level, or is multiplexed with C8_B, depending upon the MUX_MODE logic state.
When MUX_MODE = High, this pin provides an access to either card A or B C8 channel
by means of CARD_SEL selection bit.
The associated pull up resistor is either connected to V
disconnected when EN_RPU = Low.
The signal present on this pin comes from either the MCU master clock, or from any
signal fulfilling the logic level and frequency specifications. This signal is fed to the
internal clock selection circuit prior to be connected to the external smart card #A. Each
of the external card can have different division ratio, depending upon the state of the
CRD_SEL pin and associated programming bits. The built−in circuit can be programmed
to 1/1, 1/2, 1/4 or 1/8 frequency division ratio.
This input is valid and routed to either CRD_CLK_A _DIVIDER or
CRD_CLK_B_DIVIDER regardless of the MUX_MODE state, depending upon the
CLK_D_A/CRD_D_B and CARD_SEL programmed states (Table 1).
Although this input supports the signal coming from a crystal oscillator, care must be
observed to avoid digital levels outside the specified V
clock signal shall have rise and fall times compatible with the operating frequency.
This pin is the ground reference for both analog and digital signals and must be
connected to the system Ground. Care must be observed to provide a copper PCB layout
designed to avoid small signals and power transients sharing the same track. Good high
frequency techniques are strongly recommended.
The signal present on this pin comes from either the MCU master clock, or from any
signal fulfilling the logic level and frequency specifications. This signal is fed to the
internal clock selection circuit prior to be connected to the external smart card #B. Each
of the external card can have different division ratio, depending upon the state of the
CRD_SEL pin and associated programming bits. The built−in circuit can be programmed
to 1/1, 1/2, 1/4, or 1/8 frequency division ratio.
This input is valid and routed to either CRD_CLK_B_DIVIDER or CRD_CLK_A_DIVIDER
regardless of the MUX_MODE state, depending upon the CRD_D_B/CRD_D_A and
CARD_SEL programmed states (Table 1).
Although this input supports the signal coming from a crystal oscillator, care must be
observed to avoid digital levels outside the specified V
clock signal shall have rise and fall times compatible with the operating frequency.
This pin controls the card #B C8 contact. The signal can be either de −multiplexed, at
MPU level, or is multiplexed with C8_A, depending upon the MUX_MODE logic state.
When MUX_MODE = High, this pin is internally disable, a pull up resistor is connected to
V
by C8_A associated with CARD_SEL selection bit.
The associated pull up resistor is either connected to V
disconnected when EN_RPU = Low.
This pin controls the card #B C4 contact. The signal can be either de −multiplexed, at
MPU level, or is multiplexed with C8_A, depending upon the MUX_MODE logic state.
When MUX_MODE = High, this pin is internally disable, a pull up resistor is connected to
V
C4_A associated with CARD_SEL selection bit.
The associated pull up resistor is either connected to V
disconnected when EN_RPU = Low.
CC
CC
, (regardless of the logic state of EN_RPU), and the access to card B takes place by
(regardless of the logic state of EN_RPU is), and the access to card B takes place
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NCN6004A
5
Description
IH
IH
CC
CC
CC
CC
CC
/V
/V
(EN_RPU = H) or
(EN_RPU = H) or
(EN_RPU = H) or
IL
IL
(EN_RPU = H) or
(EN_RPU = H) or
range. Similarly, the input
range. Similarly, the input