pdi1394p23 NXP Semiconductors, pdi1394p23 Datasheet - Page 19

• Manufacturer Part Number: pdi1394p23
• Description: 2-port/1-port 400 Mbps Physical Layer Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions
2001 Sep 06
Link_Speed
Bridge_Aware
2-port/1-port 400 Mbps physical layer interface
FIELD
SIZE
2
2
Rd/Wr
Rd/Wr
TYPE
of the value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset.
(PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to
Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
This field is replicated in the “sp” field of the self-ID packet to indicate the speed capability of the node
peer PHYs during self-ID; the PDI1394P23 PHY identifies itself as S400 capable to its peers regardless
An 11b can be written into this field, however, a 10b will be sent in the self-ID packet.
Bridge_Aware. This field reports Bridge_Aware capability to all nodes via the self-ID packet. Encoding
is as follows:
This field is replicated in bits 18 and 19 of the self-ID packet. The value of this field does not affect PHY
operation. It is a reporting mechanism. The default value for this field is set by the BRIDGE pin. The
BRIDGE pin is sampled during a hardware reset (RESET low). When the BRIDGE pin is low, this field
is set to “00” indicating a “non-bridge device.” When the BRIDGE pin is high, this field is set to “11”
indicating a “1394.1 bridge compliant” device. Writing to this field overrides the default setting by the
BRIDGE pin.
Code
Code
00
01
10
11
00
01
10
11
Speed
illegal
S100
S200
S400
Meaning
Non-bridge device
Reserved (BRAN Bridge)
Bridge compliant with 1394.1 (unchanged state)
Bridge compliant with 1394.1 (changed state)
19
DESCRIPTION
PDI1394P23
Preliminary data