pdi1394p23 NXP Semiconductors, pdi1394p23 Datasheet - Page 27

• Manufacturer Part Number: pdi1394p23
• Description: 2-port/1-port 400 Mbps Physical Layer Interface
• Manufacturer: NXP Semiconductors

indicate the type of the request. In the descriptions below, bit 0 is the
Philips Semiconductors
18.1 LLC service request
To request access to the bus, to read or write a PHY register, or to
control arbitration acceleration, the LLC sends a serial bit stream on
the LREQ terminal as shown in Figure 14.
The length of the stream will vary depending on the type of request
as shown in Table 11.
Table 11. Request Stream Bit Length
Regardless of the type of request, a start bit of 1 is required at the
beginning of the stream, and a stop bit of 0 is required at the end of
the stream. The second through fourth bits of the request stream
most significant, and is transmitted first in the request bit stream.
The LREQ terminal is normally low.
Encoding for the request type is shown in Table 12.
Table 12. Request Type Encoding
2001 Sep 06
Bus request
Read register request
Write register request
Acceleration control request
LR1–LR3
2-port/1-port 400 Mbps physical layer interface
000
001
010
011
100
101
110
111
REQUEST TYPE
ImmReq
IsoReq
PriReq
FairReq
RdReg
WrReg
AccelCtl
Reserved
NAME
LR0
Immediate bus request. Upon
detection of idle, the PHY takes
control of the bus immediately
without arbitration
Isochronous bus request. Upon
detection of idle, the PHY arbitrates
for the bus without waiting for a
subaction gap.
Priority bus request. The PHY
arbitrates for the bus after a
subaction gap, ignores the fair
protocol.
Fair bus request. The PHY
arbitrates for the bus after a
subaction gap, follows the fair
protocol
The PHY returns the specified
register contents through a status
transfer.
Write to the specified register.
Enable or disable asynchronous
arbitration acceleration.
Reserved.
LR1
DESCRIPTION
NUMBER OF BITS
7 or 8
17
9
6
Figure 14. LREQ Request Stream
LR2
27
LR3
For a bus request the length of the LREQ bit stream is 7 or 8 bits, as
shown in Table 13.
Table 13. Bus Request
The 3-bit request speed field used in bus requests is shown in
Table 14.
Table 14. Bus Request Speed Encoding
NOTE:
The PDI1394P23 will accept a bus request with an invalid speed
code and process the bus request normally. However, during packet
transmission for such a request, the PDI1394P23 will ignore any
data presented by the LLC and will transmit a null packet.
For a read register request, the length of the LREQ bit stream is
9 bits as shown in Table 15.
Table 15. Read Register Request
BIT(S)
BIT(S)
1–3
4–6
1–3
4–7
0
7
0
8
Start Bit
Request Type
Address
Stop Bit
Start Bit
Request Type
Request Speed
Stop Bit
LR4–LR6
All others
NAME
NAME
000
010
100
Indicates the beginning of the transfer
(always 1).
A 100 indicating this is a read register
request.
Identifies the address of the PHY register
to be read.
Indicates the end of the transfer
(always 0).
Indicates the beginning of the transfer
(always 1).
Indicates the type of bus request. See
Table 12.
Indicates the speed at which the PHY
will send the data for this request. See
Table 14 for the encoding of this field.
Indicates the end of the transfer
(always 0). If bit 6 is 0, this bit may be
omitted.
LR(n–2)
DESCRIPTION
DESCRIPTION
PDI1394P23
DATA RATE
Invalid
S100
S200
S400
LR(n–1)
SV01758
Preliminary data