hd64338342hw Renesas Electronics Corporation., hd64338342hw Datasheet - Page 431

• Manufacturer Part Number: hd64338342hw
• Description: Renesas 8-bit Single-chip Microcomputer H8 Family/h8/300l Super Low Power Series
• Manufacturer: Renesas Electronics Corporation.

Figure 10.20 shows an example of a flowchart for a simultaneous transmit/receive operation. This
procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Simultaneous transmit/receive
Figure 10.20 Example of Simultaneous Data Transmission/Reception Flowchart
3
1
2
transmission/reception?
Sets bits SPC31 and
SPC32 to 1 in SPCR
Read receive data
Clear bits TE and
RE to 0 in SCR3
Read bit TDRE
Read bit RDRF
Continue data
Write transmit
Read bit OER
data to TDR
TDRE = 1?
RDRF = 1?
OER = 1?
in SSR
in RDR
in SSR
in SSR
Start
End
Yes
No
Yes
No
4
Yes
No
No
Yes
Notes: 1. When switching from transmission to simultaneous
Overrun error
processing
(Synchronous Mode)
2. When switching from reception to simultaneous transmission/reception,
transmission/reception, check that SCI3 has finished transmitting and
that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set
bits TE and RE to 1.
check that SCI3 has finished receiving, clear bit RE to 0, then check
that bit RDRF and the error flags (OER, FER, and PER) are cleared to
0, and finally set bits TE and RE to 1.
1.
2.
3.
4.
Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before receiving the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmis-
sion and reception cannot be resumed if bit
OER is set to 1.
See figure 10-18 for details on overrun error
processing.
Section 10 Serial Communication Interface
Rev. 6.00 Aug 04, 2006 page 395 of 680
REJ09B0145-0600