tc58nvg0s3eta00 TOSHIBA Semiconductor CORPORATION, tc58nvg0s3eta00 Datasheet - Page 28

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tc58nvg0s3eta00

Manufacturer Part Number
tc58nvg0s3eta00
Description
1 Gbit 128m ? 8 Bit Cmos Nand E2prom
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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1024 blocks
65536
pages
Schematic Cell Layout and Address Assignment
Table 1. Addressing
First cycle
Second cycle
Third cycle
Fourth cycle
Data Cache
Page Buffer
The Program operation works on page units while the Erase operation works on block units.
2048
2048
2112
PA15
CA7
I/O8
PA7
L
PA14
64
64
I/O7
CA6
PA6
L
PA13
CA5
PA5
8I/O
I/O6
L
I/O8
64 Pages = 1 block
PA12
CA4
I/O5
PA4
L
I/O1
CA11 CA10
PA11
I/O4
CA3
PA3
28
A page consists of 2112 bytes in which 2048 bytes are
used for main memory storage and 64 bytes are for
redundancy or for other uses.
consecutive clock cycles, as shown in Table 1.
PA10
I/O3
CA2
PA2
An address is read in via the I/O port over four
1 page = 2112 bytes
1 block = 2112 bytes × 64 pages = (128K + 4K) bytes
Capacity = 2112 bytes × 64pages × 1024 blocks
CA1
CA9
I/O2
PA1
PA9
I/O1
CA0
CA8
PA0
PA8
CA0 to CA11: Column address
PA0 to PA15: Page address
PA6 to PA15: Block address
PA0 to PA5: NAND address in block
TC58NVG0S3ETA00
2010-01-25C

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