tc58nvg0s3eta00 TOSHIBA Semiconductor CORPORATION, tc58nvg0s3eta00 Datasheet - Page 37

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tc58nvg0s3eta00

Manufacturer Part Number
tc58nvg0s3eta00
Description
1 Gbit 128m ? 8 Bit Cmos Nand E2prom
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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Multi Page Program
Multi Page Program
I/O0~7
R/ B
Data
Input
The device has a Multi Page Program, which enables even higher speed program operation compared to Auto Page Program. The sequence of command, address and data
input is shown bellow. (Refer to the detailed timing chart.)
Although two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to “1” when
any of the pages fails. Limitation in addressing with Multi Page Program is shown below.
NOTE: Any command between 11h and 81h is prohibited except 70h and FFh.
80h
80h
Address & Data Input
CA0~CA11
PA0~PA5
PA6
PA7~PA15
(512 Block)
Block 1020
Block 1022
Plane 0
Block 0
Block 2
: Valid
: Valid’
: District0’
: Valid’
11h
11h
tDCBSYW1
Note
81h
81h
(512 Block)
Block 1021
Block 1023
Address & Data Input
Plane 1
Block 3
Block 1
CA0~CA11
PA0~PA5
PA6
PA7~PA15
: Valid
: Valid
: District1
: Valid
10h
10h
tPROG
37
70h
I/O0
Fail
”1”
”0”
Pass
TC58NVG0S3ETA00
2010-01-25C

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