lm2633mtd National Semiconductor Corporation, lm2633mtd Datasheet - Page 23

• Manufacturer Part Number: lm2633mtd
• Description: Advanced Two-phase Synchronous Triple Regulator Controller For Notebook Cpus
• Manufacturer: National Semiconductor Corporation

Operation Descriptions
FET current. Once the bottom FET current flows from drain
to source, the bottom FET will be turned off. This prevents
negative inductor current. In force-PWM operation, the in-
ductor current is allowed to go negative, so the regulator is
always in Continuous Conduction Mode (CCM), no matter
what the load is. In CCM, the steady-state duty cycle is
almost independent of the load, and is roughly V
by V
ous Conduction Mode (DCM) under light load. Once the
regulator enters DCM, its steady-state duty cycle droops as
the load current decreases. The regulator operates in DCM
PWM mode until its duty cycle falls below 85% of the CCM
duty cycle, when the MIN_ON_TIME comparator takes over.
It forces 85% CCM duty cycle which causes the output
voltage to continuously rise and COMPx pin voltage (error
amplifier output voltage) to continuously droop. When the
COMPx pin voltage dips below 0.5V, the CYCLE_SKIP com-
parator toggles, causing the present switching cycle to be
’skipped’, i.e., both FETs remain off during the whole cycle.
As long as the COMPx pin voltage is below 0.5V, no switch-
ing of the FETs will happen. As a result, the output voltage
will droop, and the COMPx pin voltage will rise. When the
COMPx pin goes above 0.5V, the CYCLE_SKIP comparator
flips and allows a 85% CCM duty cycle pulse to happen. If
the load current is so small that this single pulse is enough to
bring output voltage up to such a level that the COMPx pin
drops below 0.5V again, the pulse skipping will happen
again. Otherwise it may take a number of consecutive pulses
to bring the COMPx pin voltage down to 0.5V again. As the
load current increases, it takes more and more consecutive
pulses to discharge the COMPx voltage to 0.5V. When the
load current is so high that the duty cycle exceeds the 85%
CCM duty cycle, then pulse-skipping disappears. In
pulse-skip mode, the frequency of the switching pulses de-
creases as the load current decreases.
The LM2633 needs to sense the output voltages directly in
the pulse-skip mode operation. For Channel 1 this is realized
through the FB1 pin. For Channel 2, it is realized by con-
necting SENSE2 pin to the output.
The LM2633 pulse-skip mode helps the light load efficiency
for two reasons. First, it does not turn on the bottom FET, this
eliminates circulating energy and reduces gate drive power
loss. Second, the top FET is only turned on when necessary,
rather than every cycle, which also reduces gate drive power
loss.
Current Sensing and Current Limiting
Sensing of the inductor current for feedback control is ac-
complished through sensing the drain-source voltage of the
top FET when it is turned on. There is a leading edge
blanking circuitry that forces the top FET to be on for at least
160ns. Beyond this minimum on time, the output of the PWM
comparator is used to turn off the top FET. The blanking
circuitry is being used to blank out the noise associated with
the turning on of the top FET.
Current limit is implemented using the same V
See Figure 1 .
IN
. In pulse-skip mode, the regulator enters Discontinu-
(Continued)
ds
information.
OUT
divided
23
There is a 10 µA current sink on the ILIMx pin. When an
external resistor is connected between ILIMx pin and top
FET drain, a DC voltage is established between the two
nodes. When the top FET is turned on, the voltage across
the FET is proportional to the inductor current. If the inductor
current is too high, SWx pin voltage will be lower than the
ILIMx voltage, causing the comparator to toggle and thus the
top FET will be turned off immediately. The comparator is
disabled when the top FET is turned off and during the
leading edge blanking time.
Negative Current Limit
The negative current limit is put in place to ensure that the
inductor will not saturate during a negative current flow and
cause excessive current to flow through the bottom FET. The
negative current limit is realized through sensing the bottom
FET V
with the bottom FET Vds when it is on. Upon seeing too high
a Vds, the bottom FET will be turned off. The negative
current limit is activated in force PWM mode, or in the case
of Channel 1, also whenever there is a dynamic VID change.
Active Frequency Control
As the input / output voltage differential increases, the on
time of the top FET as regulated by the feed-back control
circuitry may approach the minimum value, i.e. the blanking
time. That will cause unstable operations such as pulse
skipping and uneven duty cycles. To avoid such an issue, the
LM2633 is designed in such a way that when input voltage
rises above about 17V, the PWM frequency starts to droop.
The frequency droops fairly linearly with the input voltage.
See typical curves. The theoretical equation for PWM fre-
quency is ƒ = min (1, 17V/V
The main impact of this shift in PWM frequency is the
inductor ripple current and output ripple voltage. Regulator
design should take this into account.
Shutdown Latch State
This state is typically caused by an output under voltage or
over voltage event. In this state, both switching channels
have their top FETs turned off, and their bottom FETs turned
on. The linear channel is not affected.
There are two methods to release the system from the latch
state. One is to create a fault state (see the corresponding
section) by either bringing down the input voltage to below
3.9V UVLO threshold and then bringing it back to above
4.2V, or somehow by causing the system to enter thermal
shut down. Another method is to pull both ON/SSx pins
below 0.8V and then release them.
After the latch is released, the two switching channels will go
through the normal soft start process. The linear channel
ds
. An internal reference voltage is used to compare
FIGURE 1. Current Limit Method
IN
) x 250 kHz.
20000805
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