lm2633mtd National Semiconductor Corporation, lm2633mtd Datasheet - Page 28

• Manufacturer Part Number: lm2633mtd
• Description: Advanced Two-phase Synchronous Triple Regulator Controller For Notebook Cpus
• Manufacturer: National Semiconductor Corporation

www.national.com
Output Inductor Selection
be a good idea to adjust the inductance value so that a
requirement of 3.2 capacitors can be reduced to 3 capaci-
tors.
Inductor ripple current is often the criterion for selecting an
output inductor. However, in the CPU core or GTL bus
application, it is usually of lower priority. That is partly be-
cause the stringent output ripple voltage requirement auto-
matically limits the inductor ripple current level. It is never-
theless a good idea to double check the ripple current. The
equation is:
where min(V
17V.
What is more important is the ripple content, which is defined
by I
less than 50% is ok. Too high a ripple content will cause too
much loss in the inductor.
Example: V
If the maximum load current is 14A, then the ripple content is
4.3A / 14A = 30%.
When choosing the inductor, the saturation current should
be higher than the maximum peak inductor current. The
RMS current rating should be higher than the maximum load
current.
MOSFET Selection
Bottom FET Selection
During normal operations, the bottom FET is turned on and
off at almost zero voltage. So only conduction loss is present
in the bottom FET. The bottom FET power loss peaks at the
maximum input voltage and load current. The most important
parameter when choosing the bottom FET is the on resis-
tance. The less the on resistance, the less the power loss.
The equation for the maximum allowed on resistance at
room temperature for a given FET package, is:
where T
in the FET, T
R
and TC is the temperature coefficient of the on resistance
which is typically 4000ppm/˚C.
If the calculated on resistance is smaller than the lowest
value available, multiple FETs can be used in parallel. If the
design criterion is to use the highest-R
R
ds_max
ja
rip_max
is the junction-to-ambient thermal resistance of the FET,
j_max
of each FET can be increased due to reduced
/ I
in_max
load_max
in_max
is the maximum allowed junction temperature
a_max
= 21V, V
, 17V) means the smaller of V
. Generally speaking, a ripple content of
is the maximum ambient temperature,
n
= 1.6V, f = 250kHz, L = 1.7µH.
ds
FET, then the
(Continued)
in_max
(13)
(14)
and
28
current. In the case of two FETs in parallel, multiply the
calculated on resistance by 4 to obtain the on resistance for
each FET. In the case of three FETs, that number is 9. Since
efficiency is very important in a mobile PC, having the lowest
on resistance is usually more important than fully utilizing the
thermal capacity of the package. So it is probably better to
find the lowest-R
are needed.
Example: T
V
If the lowest-on-resistance FET has a R
two can be used in parallel. The temperature rise on each
FET will not go to T
ing only half of the total power.
Alternatively, two 22m
each FET reaching T
will double the bottom switch power loss.
Top FET Selection
The top FET has two types of power losses - the switching
loss and the conduction loss. The switching loss mainly
consists of the cross-over loss and the bottom diode reverse
recovery loss. It is rather difficult to estimate the switching
loss. A general starting point is to allot 60% of the top FET
thermal capacity to switching loss. The best way to find out is
still to test it on bench. The equation for calculating the on
resistance of the top FET is thus:
where T
in the FET, T
R
and TC is the temperature coefficient of the on resistance
which is typically 4000ppm/˚C.
Example: T
V
Since the switching loss usually increases with bigger FETs,
choosing a top FET with a much smaller on resistance
sometimes may not yield noticeable lower temperature rise
and better efficiency.
It is recommended that the peak value of the V
FET does not exceed 200 mV when the top FET conducts,
otherwise the COMPx pin voltage may reach its high clamp
value (2V) and cause loss of regulation.
in_max
in_min
ja
is the junction-to-ambient thermal resistance of the FET,
= 14V, V
= 21V, V
j_max
j_max
j_max
is the maximum allowed junction temperature
a_max
n
ds
n
= 100˚C, T
= 100˚C, T
= 1.6V, and I
= 1.6V, and I
FET first, and then determine how many
j_max
is the maximum ambient temperature,
j_max
because each FET is now dissipat-
FETs can be used in parallel, with
. This may lower the FET cost, but
a_max
a_max
load_max
load_max
= 60˚C, R
= 60˚, R
ds_max
= 10A.
= 10A.
of 10m , then
ja
ja
ds
= 60˚C/W,
= 60˚C/W,
of the top
(15)