lm2633mtd National Semiconductor Corporation, lm2633mtd Datasheet - Page 38

• Manufacturer Part Number: lm2633mtd
• Description: Advanced Two-phase Synchronous Triple Regulator Controller For Notebook Cpus
• Manufacturer: National Semiconductor Corporation

www.national.com
Control Loop Design
where V
non-inverting input of the error amplifier and has a typical
value of 1.24V, and I
pin and has a typical value of 70 nA.
Example: The intended output voltage is 2.5V. Find the
appropriate R
The G3 voltage cannot exceed 4V, and the G3 current
sourcing capability decreases with increasing G3 pin volt-
age. See the typical curves. It is suggested that the maxi-
mum output voltage does not exceed 3V when an NPN pass
transistor is used. If an N-channel FET is to be used, make
sure the FET can be fully turned on before G3 goes to 4V.
There are two factors to consider when selecting Q
the DC current gain , second is power dissipation.
For a certain load current, the lower the
base current is necessary to maintain regulation. Since the
base current comes from VIN pin through internal linear
regulation, a large base current significantly increases power
consumption in the LM2633 and hurts light-load efficiency,
particularly when VIN is relatively high. Therefore a transistor
with a large
The maximum power consumption in Q
Example: The input voltage of the linear regulator is 3.3V
voltage is 2.5V. Since Channel 3 of the LM2633 has a
tolerance over temperature, and the voltage divider contrib-
utes another
when a voltage divider is used.
If the ambient temperature is 65˚C or less, a SOT-23 pack-
age should be able to handle this much power.
Since Channel 3 affects UVP, if it is not to be used, proper
termination of the pins should be made. One good way is to
tie FB3 to VLIN5, and tie OUT3 and G3 together and leave
them floating. See Figure 20 .
±
±
P
5%, the maximum load current is 150 mA, and the output
3%. See Equation (52) for the calculation of total tolerance
loss
= 150 mA x (3.3V x 1.05 − 2.5V x 0.97) = 156 mW
fb3
P
FIGURE 20. When Ch.3 is Not in Use
is equal to the reference voltage connected to the
loss
2
±
value is preferred.
1%, so the total output voltage tolerance is
value if R
= I
load_max
fb3
is the bias current drawn by the FB3
1
is chosen to be 10.0 k .
• (V
in2_max
(Continued)
− V
1
200008A8
is:
out3_min
value, the more
)
1
. First is
±
(61)
(62)
(63)
2%
38
The error amplifier of Channel 3 has a DC gain of 83 dB, and
a unity-gain bandwidth of 200 kHz. See the plots in Figure
21 .
It is not easy to model the loop frequency response of an
NPN linear regulator. The best way is still to measure the
loop gain under different load conditions on bench. As a
reference point, for an LDO set at 2.5V that uses an
MMBT2222 as the pass transistor, a 1 µF ceramic as the
output capacitor and at a 170 mA load, the bandwidth is
about 107 kHz, with a phase margin of 71˚ and a gain margin
of about 10 dB.
The higher the bandwidth, the less the output capacitance is
needed to handle the load transient. However, for most
applications, stability is the only concern.
PCB Layout Guidelines
It is extremely important to follow the guidelines below to
ensure a clean and stable operation.
1. Use a four-layer PCB.
2. Keep the FETs as close to the IC as possible.
3. Keep the power components on the right side (pins 25
4. Analog ground and power ground should be separate
5. The VDDx pin decoupling capacitor should be con-
6. Input ceramic capacitors should be placed very close to
7. HDRVx, SWx traces should be as close to each other as
8. Keep KSx trace as short as possible. Otherwise, use a
9. ILIMx trace should be kept away from noisy nodes such
10. It is preferable to have a shorter and wider FBx trace
FIGURE 21. V
through 48) of the IC and low-power components on the
left side.
planes and should be connected at a single point, pref-
erably at the PGNDx and GND pins and directly under-
neath the IC.
nected to the power ground plane.
the FETs and their connections to the drain of the top
FET and to the source of the bottom FET should be as
short as possible and should not go through power plane
or ground plane.
possible to minimize noise emission. If these two traces
are longer than 2 centimeters, they should be fairly wide,
such as 50mil.
trace of 50mil or wider.
as the switch node.
than a longer and narrower one.
FB3
-to-V
G3
Transfer Function (theoretical)
20000895