tza3012ahw NXP Semiconductors, tza3012ahw Datasheet - Page 11

• Manufacturer Part Number: tza3012ahw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-ratetm Fibre Optic Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Fractional N synthesizer
The DCR uses a fractional N-type synthesizer to provide
the A-rate functionality that allows the DCR to synchronize
to incoming data, regardless of its bit rate.
The DCR has a 22-bit fractional N capability which allows
any combination of bit rate and reference frequency
between 18
2003 May 21
division factor. The LSB (bit k[0]) of the fractional divider,
should be set to logic 1 to avoid limit cycles. These are
cycles of less than maximum length that generate spurs in
the frequency spectrum. This leaves 21 bits (k[21:1])
available for programming the fraction, allowing a
resolution frequency of approximately 10 Hz at a fixed
reference frequency.
Programming the reference clock
Pre-programmed operation requires a reference clock
frequency of between 18 and 21 MHz connected to
pins CREF and CREFQ. However, to obtain the bit rates in
Table 3, the reference clock frequency must be
19.44 MHz. For SDH/SONET applications, a reference
clock frequency of 19.44
handbook, full pagewidth
30 Mbits/s up to 3.2 Gbits/s
A-rate
CREF(Q)
DATA IN
R and 21
fibre optic receiver
N [ 8:0 ]
CALCULATOR
FRACTION
9
REFERENCE
R MHz, where R is the reference
K [ 21:0 ]
INPUT
R MHz is preferred.
22
AMPLIFIER
LIMITING
REFERENCE
OCTAVE
DIVIDER
DIVIDER
DIVIDER
Fig.6 Block diagram of data and clock recovery.
MAIN
R
M
N
DATA PHASE
FREQUENCY
CONTROLLED
DETECTOR
DETECTOR
OSCILLATOR
WINDOW
VOLTAGE
(VCO)
11
I
reference clock frequency ranges to be selected by
programming reference divider R using bits REFDIV in
I
The REFDIV bit settings, reference clock frequency
ranges, and division factor are shown in Table 7.
The reference frequency is always divided internally to the
lowest range of 18 to 21 MHz.
Table 7 Truth table for bits REFDIV in I
2
2
REFDIV
down
down
C-bus control operation allows any one of four possible
C-bus register DCRCNF (address B6 H).
up
up
00
01
10
11
CHARGE PUMP
CHARGE PUMP
LOOP FILTER
DCRCNF
RECOVERED CLOCK
RECOVERED DATA
DIVISION
FACTOR
PRESCALER
OUTPUT
R
1
2
4
8
FREQUENCY
REFERENCE
SDH/SONET
155.52
DOUT(Q)
COUT(Q)
(MHz)
19.44
38.88
77.76
MGU346
PRSCLO(Q)
TZA3012AHW
Product specification
to
DEMULTIPLEXER
2
C-bus register
FREQUENCY
REFERENCE
144 to 168
RANGE
18 to 21
36 to 42
72 to 84
(MHz)