tza3012ahw NXP Semiconductors, tza3012ahw Datasheet - Page 2

• Manufacturer Part Number: tza3012ahw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-ratetm Fibre Optic Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FEATURES
Dual limiter features
Data and clock recovery features
Demultiplexer features
Additional features with the I2C-bus
(1) A-rate is a Trademark of Koninklijke Philips Electronics N.V.
ORDERING INFORMATION
2003 May 21
TZA3012AHW
Single 3.3 V power supply
I
Dual limiting input with 12 mV sensitivity
Received Signal Strength Indicator (RSSI)
Loss Of Signal (LOS) indicator with threshold adjust
Differential overvoltage protection.
Supports SHD/SONET bit rates at 155.52, 622.08,
2488.32 and 2666.06 Mbits/s (STM16/OC48
Supports Gigabit Ethernet at 1250 and 3125 Mbits/s
Supports Fibre Channel at 1062.5 and 2125 Mbits/s
ITU-T compliant jitter tolerance
Frequency lock indicator
Stable clock signal when input data absent
Outputs for recovered data and clock loop mode.
1:16, 1:10, 1:8 or 1:4 demultiplexing ratio
LVPECL or CML demultiplexer outputs
Frame detection for SDH/SONET and GE frames
Parity bit generation
Loop mode inputs to demultiplexer.
A-rate
3.2 Gbits/s with one reference frequency
Programmable frequency resolution of 10 Hz
Four reference frequency ranges
Adjustable swing of data, clock and parallel outputs
Programmable polarity of all RF I/Os
30 Mbits/s up to 3.2 Gbits/s
A-rate
2
NUMBER
C-bus and pin programmable fibre optic receiver.
TYPE
TM(1)
supports any bit rate from 30 Mbits/s to
fibre optic receiver
HTQFP100
NAME
plastic thermal enhanced thin quad flat package; 100 leads;
body 14
14
FEC)
1 mm; exposed die pad
2
DESCRIPTION
APPLICATIONS
GENERAL DESCRIPTION
The TZA3012AHW is a fully integrated optical network
receiver containing a dual limiter, Data and Clock
Recovery (DCR) and a demultiplexer with demultiplexing
ratios 1:16, 1:10, 1:8 or 1:4.
The A-rate feature allows the IC to operate at any bit rate
between 30 Mbits/s and 3.2 Gbits/s using a single
reference frequency. The receiver supports loop modes
with serial clock and data inputs and outputs. All clock
signals are generated using a fractional N synthesizer with
10 Hz resolution giving a true, continuous rate operation.
For full configuration flexibility, the receiver is
programmable by pin or via the I
PACKAGE
Exchangeable pin designations of RF clock with data for
all I/Os for optimum connectivity
Reversible pin designations of parallel data bus bits for
optimum connectivity
Slice level adjustment to improve Bit Error Rate (BER)
Mute function for a forced logic 0 output state
Programmable parity
Programmable 32-bit frame detection.
Any optical transmission system with bit rates between
30 Mbits/s and 3.2 Gbits/s
Physical interface IC in receive channels
Transponder applications
Dense Wavelength Division Multiplexing (DWDM)
systems.
2
TZA3012AHW
C-bus.
Product specification
SOT638 1
VERSION