tza3012ahw NXP Semiconductors, tza3012ahw Datasheet - Page 17

• Manufacturer Part Number: tza3012ahw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-ratetm Fibre Optic Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
If ENBA is LOW, no active alignment takes place.
However, if the frame header pattern occurs in the
formatted data, a frame pulse will still be output on pins FP
and FPQ.
For 10-bit oriented protocols, such as Gigabit Ethernet,
the frame header detection operates on a 10-bit pattern
sequence. These 10 bits should be programmed into
I
HEADER2; the remaining 22 bits are ignored. A ‘don’t
care’ pattern overlay can be programmed in I
register HEADERX3 and the two MSBs of HEADERX2.
Since some 10-bit oriented protocols use a DC balancing
code, the detection pattern could appear in
complementary form in the data stream. By setting
bit CMPL in I
header detection scans the data stream for both the
programmed pattern and its complement simultaneously.
Either occurrence produces a ‘byte’ alignment and a
corresponding frame pulse on pins FP and FPQ.
The default pattern (after power-up) is ‘0011111010’ or
K28.5 character plus alternating 010. This is the only
pattern containing five consecutive bits of the same sign.
2003 May 21
handbook, full pagewidth
2
C-bus registers HEADER3 and the two MSBs of
30 Mbits/s up to 3.2 Gbits/s
A-rate
‘X’ = “don’t care”
‘MSB’ = Most Significant Byte.
2
C-bus register DMXCNF (address A8H), the
fibre optic receiver
HEADER3
HEADERX3
received
data
BIT32
Fig.9 Example of programming the frame header pattern.
X
0
1
0
0
0
MSB HEADER
0
0
0
1
0
1
0
0
0
2
C-bus
X
1
1
1
0
1
1
0
1
data stream
17
Receiver framing in SDH/SONET applications
Figure 10 shows a typical SDH/SONET reframe sequence
involving byte alignment. Frame and byte boundary
detection is enabled on the rising edge of ENBA and
remains enabled while ENBA is HIGH. Boundaries are
recognized on receipt of the second A2 byte and FP goes
HIGH for one POCLK cycle.
In 1:16 mode, the first two A2 bytes in the frame header
are the first data word to be reported with the correct
alignment on the outgoing data bus (D00 to D15). In 1:8
mode the first A2 byte is the first aligned data byte (D04 to
D11), while in 1:4 mode the most significant nibble of the
first A2 byte is the first aligned data (D06 to D09).
When interfacing with a section terminating device, ENBA
must remain HIGH for a full frame after the initial frame
pulse. This is to allow the section terminating device to
verify internally that frame and byte alignment are correct;
see Fig.11. Byte boundary detection is disabled on the first
FP pulse after ENBA has gone LOW.
Figure 12 shows frame and byte boundary detection
activated on the rising edge of ENBA, and deactivated by
the first FP pulse after ENBA has gone LOW.
0
0
0
1
0
1
LSB HEADER
1
0
1
0
0
0
0
0
0
0
0
0
1
1
X
BIT1
X
MGU548
0
1
HEADER0
HEADERX0
TZA3012AHW
Product specification