tza3012ahw NXP Semiconductors, tza3012ahw Datasheet - Page 16

• Manufacturer Part Number: tza3012ahw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-ratetm Fibre Optic Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Making pin ENBA HIGH automatically aligns the parallel
output into logical bytes or words. The same function is
implemented by setting bit ENBA in I
register DMXCNF (address A8H).
To support most commonly used transmission systems
and protocols, the demultiplexing ratio can be set to 1:16,
1:10, 1:8, and 1:4, and the frame header pattern
programmed to any 32 or 10-bit pattern; see Section
“Frame detection”.
If required, the demultiplexer output can be forced into a
fixed logic 0 state by bit DMXMUTE in I
register DMXCNF.
Adjustable demultiplexing ratio
For optimum layout connectivity, the physical positions of
parallel data bus pins D00 to D15 and D00Q to D15Q on
the chip are located either side of pin V
The number of parallel data bus outputs that are used
Table 11 Setting demultiplexing ratio
Frame detection
Byte alignment is enabled if the Enable Byte Alignment
input (pin ENBA) is HIGH, or if bit I2CENBA and bit ENBA
are both logic 1 in I
(address A8H). Whenever the incoming data has a 32-bit
or 10-bit sequence that matches the programmed frame
header pattern, the data is formatted into logical bytes or
words, and a frame pulse is generated on differential
outputs FP and FPQ. Any frame header pattern can be
programmed in I
to HEADER3.
2003 May 21
30 Mbits/s up to 3.2 Gbits/s
A-rate
PIN DMXR1
HIGH
HIGH
LOW
LOW
fibre optic receiver
2
C-bus registers HEADER0
2
C-bus register DMXCNF
PIN DMXR0
HIGH
HIGH
LOW
LOW
2
C-bus
EE
2
C-bus
(pin 63).
(REG DMXCNF)
BITS DMXR
00
01
10
11
16
depends on the demultiplexing ratio selected by
pins DMXR0 and DMXR1 or by bits DMXR in I
register DMXCNF (address A8 H). Any unused parallel
data bus outputs are disabled. The configuration settings
and active outputs for each demultiplexing ratio are shown
in Table 11.
In I
is 16:1.
To allow optimum layout connectivity, the pin designations
of the parallel data bus bits can be reversed so that the
default designated pin for D15 (MSB) is exchanged with
the default designated pin for D0 (LSB). This is
implemented by bit BUSSWAP in I
register DMXCNF (address A8H).
The highest supported speed for the parallel data bus is
400 Mbits/s. Therefore a demultiplexing ratio of 4:1 will
support bit rates of up to 1.6 Gbits/s.
Any bit position can be programmed with a ‘don’t care’ to
give a frame header pattern that is either much shorter
than 32 or 10 bits, or has gaps. The “don’t care” bits are
produced by programming a pattern into I
HEADERX0 to HEADERX3 which is used to mask the
programmed frame header pattern as shown in the
example Fig.9.
The default frame header pattern is F6F62828H,
corresponding to the middle section of the standard
SDH/SONET frame header (the last two A1 bytes plus the
first two A2 bytes).
2
C-bus control mode, the default demultiplexing ratio
DEMULTIPLEXING
RATIO
1:10
1:16
1:4
1:8
TZA3012AHW
2
C-bus
ACTIVE OUTPUTS
Product specification
LSB to MSB
D06 to D09
D04 to D11
D03 to D12
D00 to D15
2
C-bus registers
2
C-bus