tmp89fm42k TOSHIBA Semiconductor CORPORATION, tmp89fm42k Datasheet - Page 228

• Manufacturer Part Number: tmp89fm42k
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.4
Functions
RA005
14.4.7.3
to "0x00". The PWM1 pin returns to the level selected at T01MOD<TFF1>.
supplied is fcgck/2 [Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/2
and a pulse width of two machine cycles or more is required at both the "H" and "L" levels.
by setting T01MOD<DBE1> to "0" or enabled by setting T01MOD<DBE1> to "1".
When T001CR<T01RUN> is set to "0" during the timer operation, the up counter is stopped and cleared
When an external source clock is selected, input the clock at the TC00 pin. The maximum frequency to be
The double buffer can be used for T01+00PWM by setting T01MOD<DBE1>. The double buffer is disabled
Double buffer
・ When the double buffer is enabled
・ When the double buffer is disabled
operation, the set value is first stored in the double buffer, and T01+00PWM is not updated im-
mediately. T01+00PWM compares the previous set value with the up counter value. When the 16
× n-th overflow occurs, an INTTC01 interrupt request is generated and the double buffer set value
is stored in T01+00PWM. Subsequently, the match detection is executed using a new set value.
(the last set value) is read out, not the T01+00PWM value (the currently effective value).
is stopped, the set value is immediately stored in both the double buffer and T01+00PWM.
operation, the set value is immediately stored in T01+00PWM. Subsequently, the match detection
is executed using a new set value. If the value set to T01+00PWM is smaller than the up counter
value, the PWM1 pin is not reversed until the up counter overflows and a match detection is
executed using a new set value. If the value set to T01+00PWM is equal to the up counter value,
the match detection is executed immediately after data is written into T01+00PWM. Therefore,
the timing of changing the PWM1 pin may not be an integral multiple of the source clock. Simi-
larly, if T01+00PWM is set during the additional pulse output, the timing of changing the
PWM1 pin may not be an integral multiple of the source clock. If these are problems, enable the
double buffer.
is stopped, the set value is immediately stored in T01+00PWM.
When write instructions are executed on T00PWM and T01PWM in this order during the timer
When a read instruction is executed on T01+00PWM (T00REG), the value in the double buffer
When write instructions are executed on T00PWM and T01PWM in this order while the timer
When write instructions are executed on T00PWM and T01PWM in this order during the timer
When write instructions are executed on T00PWM and T01PWM in this order while the timer
PWM1 pin output
(TFF0=“1”)
PWM1 pin output
(TFF0=“0”)
Figure 14-14 PWM1 Pin Output
Timer start
(Duty pulse
PWMDUTY
width)
(cycle width)
256 counts
Page 210
(Duty pulse
PWMDUTY
width)
(cycle width)
256 counts
(1 source clock)
Additional
pulse
4
[Hz] (in SLOW1/2 or SLEEP1 mode),
TMP89FM42K