tmp89fm42k TOSHIBA Semiconductor CORPORATION, tmp89fm42k Datasheet - Page 47

• Manufacturer Part Number: tmp89fm42k
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
internal high-frequency clock (fosc) and then stop either of the high-frequency clocks not to be used. If a
mode transition is made with both the external and internal high-frequency clocks enabled, the transition may
not be performed properly.
(fh)".
lation circuit can be used as general-purpose I/O ports.
(1)
(2)
(3)
Before switching the operating mode, be sure to select either the external high-frequency clock (fc) or the
For how to switch the high-frequency reference clock (fh), refer to "(1) High-frequency reference clock
In the single-clock mode, pins P02 (XTIN) and P03 (XTOUT) of the external low-frequency clock oscil-
is used as the high-frequency reference clock (fh).
clock (fcgck).
is released to the NORMAL1 mode.
after the interrupt processing is completed.
the IDLE1 mode activation instruction.
base timer.
become the same as the states when a reset is released. For operations of the peripheral circuits in the
IDLE0 mode, refer to the section of each peripheral circuit.
to the peripheral circuits except the time base timer.
is released, the timing generator starts the clock supply to all the peripheral circuits and the NORMAL1
mode is restored.
set after the NORMAL mode is restored.
the operation returns normal after the interrupt processing is completed.
In this mode, the CPU core and the peripheral circuits operate using the gear clock (fcgck).
After reset release, the NORMAL1 mode becomes active and the internal high-frequency clock (fosc)
In this mode, the CPU and the watchdog timer stop and the peripheral circuits operate using the gear
The IDLE1 mode is activated by setting SYSCR2<IDLE> to "1" in the NORMAL1 mode.
When the IDLE1 mode is activated, the CPU and the watchdog timer stop.
When the interrupt latch enabled by the interrupt enable register EFR becomes "1", the IDLE1 mode
When the IMF (interrupt master enable flag) is "1" (interrupts enabled), the operation returns normal
When the IMF is "0" (interrupts disabled), the operation is restarted by the instruction that follows
In this mode, the CPU and the peripheral circuits stop, except the oscillation circuits and the time
In the IDLE0 mode, the peripheral circuits stop in the states when the IDLE0 mode is activated or
The IDLE0 mode is activated by setting SYSCR2<TGHALT> to "1" in the NORMAL1 mode.
When the IDLE0 mode is activated, the CPU stops and the timing generator stops the clock supply
When the falling edge of the source clock selected at TBTCR<TBTCK> is detected, the IDLE0 mode
Note that the IDLE0 mode is activated and restarted, regardless of the setting of TBTCR<TBTEN>.
When the IDLE0 mode is activated with TBTCR<TBTEN> set at "1", the INTTBT interrupt latch is
When the IMF is "1" and the EF5 (the individual interrupt enable flag for the time base timer) is "1",
NORMAL1 mode
IDLE1 mode
IDLE0 mode
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TMP89FM42K