tmp89fm42k TOSHIBA Semiconductor CORPORATION, tmp89fm42k Datasheet - Page 43

• Manufacturer Part Number: tmp89fm42k
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
2.3.3.3
A quarter of the basic clock
for the low-frequency clock
SYSCR2<SYSCK>
SYSCR1<DV9CK>
peripheral circuits from the gear clock (fcgck) or the clock that is a quarter of the external low-frequency
clock (fs). The timing generator has the following functions:
Gear clock fcgck
(1)
The timing generator is a circuit that generates system clocks to be supplied to the CPU core and the
Timing generator
a machine cycle counter.
1. Generation of the main system clock (fm)
2. Generation of clocks for the timer counter, the time base timer and other peripheral circuits
The timing generator consists of a main system clock generator, a prescaler, a 21-stage divider and
Configuration of timing generator
1. Main system clock generator
2. Prescaler and divider
3. Machine cycle
frequency clock (fs) for the main system clock (fm) to operate the CPU core.
the clock that is a quarter of the external low-frequency clock (fs).
clock is switched. If the currently operating oscillation circuit is stopped before the main system
clock is switched, the internal condition becomes as shown in Table 2-1 and a system clock
reset occurs. For details of clock switching, refer to "2.3.6 Operation Mode Control".
base timer and other peripheral circuits.
of the divider becomes the output of stage 8 of the divider.
divider becomes fs/4. When SYSCR2<SYSCK> is "1", the outputs of stages 1 to 8 of the
divider and prescaler are stopped.
that follows the release of STOP mode.
Figure 2-7 Configuration of Timing Generator
This circuit selects the gear clock (fcgck) or the clock that is a quarter of the external low-
Clearing SYSCR2<SYSCK> to "0" selects the gear clock (fcgck). Setting it to "1" selects
It takes a certain period of time after SYSCR2<SYSCK> is changed before the main system
These circuits divide fcgck. The divided clocks are supplied to the timer counter, the time
When both SYSCR1<DV9CK> and SYSCR2<SYSCK> are "0", the input clock to stage 9
When SYSCR1<DV9CK> or SYSCR2<SYSCK> is "1", the input clock to stage 9 of the
The prescaler and divider are cleared to "0" at a reset and at the end of the warm-up operation
Instruction execution is synchronized with the main system clock (fm).
Prescaler
Divider
Timer counter, time base timer and other peripheral circuits
Main system clock generator
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Multiplexer
A
B
S
Y
Main system clock
fm
Divider
Machine cycle counter
TMP89FM42K