W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 101
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W83697HFFDC
Manufacturer Part Number
W83697HFFDC
Description
LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
Manufacturer
Information Storage Devices, Inc
Datasheet
1.W83697HFFDC.pdf
(167 pages)
- Current page: 101 of 167
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9.5. 3
(3) One-Time Interrupt Mode
(1) Comparator Interrupt Mode
(2) Two-Times Interrupt Mode
127'C
T
SMI#
HYST
T
OI
Temperature exceeding T
an interrupt. Once an interrupt event has occurred by exceeding T
interrupt will not occur again until the temperature exceeding T
Setting the T
Comparator Interrupt Mode. Temperature exceeds T
and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event
has occurred by exceeding T
will occur again when the next conversion has completed. If an interrupt event has occurred by
exceeding T
occur in this manner until the temperature goes below T
Setting the T
Temperature exceeding T
cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status
Register. Once an interrupt event has occurred by exceeding T
remains above the T
The W83697HF temperature sensor 1 SMI# interrupt has two modes:
O
HYST
HYST
Figure 9.8
*
and not reset, the interrupts will not occur again. The interrupts will continue to
(Temperature Hysteresis) limit to 127 ° C will set temperature sensor 1 SMI# to the
lower than T
*Interrupt Reset when Interrupt Status Registers are read
HYST
*
, the interrupt will not occur. (Figure 9.9 )
O
O
causes an interrupt and then temperature going below T
*
causes an interrupt and then temperature going below T
O
O
, then reset, if the temperature remains above the T
will set temperature sensor 1 SMI# to the Two-Times Interrupt Mode.
*
- 92 -
SMI# two time
SMI# one time
T
T
HYST
O
OI
(Over T emperature) Limit causes an interrupt
O
. (Figure 9.8 )
O .
Publication Release Date: Feb. 2002
(Figure 9.9)
O
, then reset, if the temperature
O
*
*
, then going below T
Figure 9.9
W83697HF/F
O
HYST
*
*
, the interrupt
will not cause
Revision 0.70
HYST
will also
HYST
*
*
an
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