W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 159
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W83697HFFDC
Manufacturer Part Number
W83697HFFDC
Description
LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
Manufacturer
Information Storage Devices, Inc
Datasheet
1.W83697HFFDC.pdf
(167 pages)
- Current page: 159 of 167
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CRF4 (Default 0x00)
Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to
load the value to Watch Dog Counter and start counting down. Reading this register returns current
value in Watch Dog Counter instead of Watch Dog Timer Time-out value.
CRF5 (Default 0x00)
10.12
CR30 (Default 0x00)
CR60,61(Default 0x00,0x00).
IO address:
IO address + 1 : CRF3 base address
IO address + 2 : CRF7 base address
These two registers select the GP2,3,4 base address(0x100:FFE) ON 3 bytes boundary.
Bit 7 - 0 = 0x00 Time-out Disable
Bit 7 ~ 6 : Reserved .
Bit 5
Bit 4
Bit 3 -0 : These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI.
Bit 7 ~ 3 : Reserved.
Bit 2
Bit 1
Bit 0
Logical Device 9 (GPIO Port 2 ~ GPIO Port 4 )
= 0x01 Time-out occurs after 1 second/minute
= 0x02 Time-out occurs after 2 second/minutes
= 0x03 Time-out occurs after 3 second/minutes
= 0xFF Time-out occurs after 255 second/minutes
: Force Watch Dog Timer Time-out, Write only*
= 1
: Watch Dog Timer Status, R/W
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0
................................................
: CRF1 base address
Force Watch Dog Timer time-out event; this bit is self-clearing.
Watch Dog Timer time-out occurred.
Watch Dog Timer counting
Activate GPIO4.
GPIO4 is inactive
Activate GPIO3.
GPIO3 is inactive
Activate GPIO2.
GPIO2 is inactive.
- 150 -
Publication Release Date: Feb. 2002
W83697HF/F
Revision 0.70
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