W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 146

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

CR23 (Default 0x00)
CR24 (Default 0x00)
CR25 (Default 0x00)
Bit 7 ~ 1 : Reserved.
Bit 0
Bit 7
Bit 6
Bit[5:4]
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7 ~ 4 : Reserved
Bit 3
Bit 2
Bit 1
Bit 0
: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down
mode immediately.
: Reserved.
: CLKSEL(Enable 48Mhz)
= 0
= 1
The corresponding power-on setting pin is SOUTB (pin 61).
: ROM size select
=00
=01
=10
=11
:MEMW# Select (PIN97)
= 0
= 1
:Reserved
: Enable Flash ROM Interface
= 0
= 1
This bit is read only, and set/reset by power-on setting pin. The corresponding power-on
setting pin is PENROM#(pin 52)
: PNPCSV
= 0
= 1
The corresponding power-on setting pin is DTRA# (pin 50).
: URBTRI
: URATRI
: PRTTRI
: FDCTRI.
The clock input on Pin 1 should be 24 Mhz.
The clock input on Pin 1 should be 48 Mhz.
1M
2M
4M
Reserved
MEMW# Disable
MEMW# Enable
Flash ROM Interface is enabled after hardware reset
Flash ROM Interface is disabled after hardware reset
The Compatible PnP address select registers have default values.
The Compatible PnP address select registers have no default value.
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Publication Release Date: Feb. 2002
W83697HF/F
Revision 0.70