tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 182

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TB1MOD
(0xFFFF_F192)
Name
Read/Write
Reset Value
Function
Must be written as 00.

7
0
R/W
Figure 12.8 TMRB1 Mode Register

6
0
TMRB1 Mode Register
TMP1941AF-142
Software
capture
0: Capture
1: Don’t
TB1CP0
care
Up-counter (UC1) clear control
Capture triggers
Software capture
W*
5
1
00
01
10
11
0
1
0
1
Capture triggers
00: Disabled
01: TB1IN0↑TB1IN1↑
10: TB1IN0↑TB1IN0↓
11: TA1OUT↑TA1OUT↓
Disabled
UC1 is reset upon a match with TB1RG1.
Capture disabled
Latches UC1 value into TB1CP0 at rising edges of TB1IN0
Latches UC1 value into TB1CP1 at rising edges of TB1IN1.
Latches UC1 value into TB1CP0 at rising edges of TB1IN0.
Latches UC1 value into TB1CP1 at falling edges of TB1IN0.
Latches UC1 value into TB1CP0 at rising edges of TA1OUT.
Latches UC1 value into TB1CP1 at falling edges of TA1OUT.
Latches UC1 value into TB1CP0.
Don’t care
TB1CPM1 TB1CPM0
4
0
3
0
UC1 clear
control
0: Disable
1: Enable
TB1CLE
R/W
2
0
TMP1941AF
TMRB1 clock source
00: TB1IN0 input
01: φT1
10: φT4
11: φT16
TB1CLK1
1
0
2003-03-27
TB1CLK0
0
0