tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 60

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.3.2
5.3.3
System Clock Output
configured as SCOUT (system clock output) by programming the Port 4 registers as follows:
P4CR.P44C=1 and P4FC.P44F=1. The output clock is selected through the SYSCR3.SCOSEL bit.
SCOUT.
Reducing the Oscillator Clock Drive Capability
oscillator noise and power consumption can be reduced through the programming of the SYSCR2.
the SYSCR2.DRVOSCL bit reduces the drive capability of the low-speed oscillator clock.
power-up. Both the high-speed and low-speed oscillator clocks must have a high drive capability (i.e.,
DRVOSCH=0, DRVOSCL=0) when clocking modes are changed.
Example: Switching from NORMAL mode to SLOW mode
NOTE: The phase difference between the system clock output signal (SCOUT) and the internal clock
SCOSEL = 0
SCOSEL = 1
SCOUT Select
SYSCR2.WUPT[1:0] = xx
SYSCR0.XTEN = 1
SYSCR0.WUEF = 1
Check SYSCR0.WUEF.
SYSCR1.SYSCK = 1
SYSCR0.XEN = 0
Either the fsys or fs clock can be driven out from the P44/SCOUT pin. The P44/SCOUT pin is
Table 5.2 shows the pin states in each clocking mode when the P44/SCOUT pin is configured as
When a crystal is connected between the X1 and X2 pins and/or between XT1 and XT2 pins,
Setting the SYSCR2.DRVOSCH bit reduces the drive capability of the high-speed oscillator. Setting
A reset clears both the DRVOSCH and DRVOSCL bits to 0, providing a high drive capability at
signal can not be guaranteed.
The fs clock is driven out.
The fsys clock is driven out.
NORMAL/
SLOW
Table 5.2 SCOUT Output States
TMP1941AF-20
Select warm-up period.
Enable low-speed clock (fs) oscillation.
Start warm-up period (WUP) timer.
Wait until SYSCR0.WUEF is cleared (i.e., the WUP expires.)
Switch system clock speed to low speed (fs).
Disable high-speed clock (fosc) oscillation.
IDLE
Standby Modes
SLEEP
TMP1941AF
Held at either 1 or 0.
2003-03-27
STOP