tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 349

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(9) Usage Restrictions
Overflow Exception #1
Problem:
When an overflow exception is taken, the EPC register might contain an incorrect return address, pointing
to the instruction immediately following the one that caused an overflow.
The restart location in the EPC register should be the address of the arithmetic instruction that caused the
exception, rather than the following instruction.
In the above example, the processor writes address n to the EPC register upon detection of an overflow.
However, executing the next instruction generates an interrupt at the same time, causing the processor to
rewrite the EPC register with address n+4 in the next cycle.
This problem occurs when all of these conditions are true.
•
Workarounds:
Note:
Problem-Causing Situation:
A) Software uses the ADD, ADDI or SUB instruction in the 32-bit ISA.
B) The ADD, ADDI or SUB instruction causes an overflow.
C) Another exception is requested simultaneously with the overflow.
•
•
•
n
n + 4
Instruction Pipeline
EPC Register
Toshiba’s compiler uses no instructions that could cause an overflow. Therefore, since
condition c) above never becomes true, this problem does not occur.
Before returning from the overflow exception handler, determine whether the instruction
pointed to by the EPC register caused an overflow.
Make sure that two arithmetic instructions will not appear consecutively.
Disable interrupts prior to arithmetic instructions.
You should always use one of these workarounds to avoid this problem.
Arithmetic Instruction (e.g., ADD)
Next Instruction
TMP1941AF-309
F
Detects an overflow and writes to EPC.
Detects an interrupt. Writes to EPC.
D
F
E
D
M
E
n
n + 4
W
M
TMP1941AF
W
2003-03-27